On Dec 1, 2011, at 7:38 PM, Shaohui Xie wrote: > Description of SerDes clock Bank2 setting in p2041 hardware specification > is wrong, the clock map which based on it is wrong either, so fix the > serdes clock map. > > wrong setting of SERDES Reference Clocks Bank2: > SW2[5:6] = ON OFF =>100MHz for PCI mode > SW2[5:6] = OFF ON =>125MHz for SGMII mode > > right setting of SERDES Reference Clocks Bank2: > SW2[5:6] = OFF OFF =>100MHz for PCI mode > SW2[5:6] = OFF ON =>125MHz for SGMII mode > SW2[5:6] = ON OFF =>156.25MHZ > > Signed-off-by: Shaohui Xie <[email protected]> > --- > board/freescale/p2041rdb/p2041rdb.c | 25 +++++++++++++++---------- > 1 files changed, 15 insertions(+), 10 deletions(-)
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