The current implementation invalidates the cache instead of flushing
it. This causes problems on platforms where the spl/u-boot is already
loaded to the RAM, with caches enabled by a first stage bootloader.
The V bit of the cp15's control register c1 is set to the value of
VINITHI on reset. Do not clear this bit by default, as there are SOC's
with no valid memory region at 0x0.
Signed-off-by: Sughosh Ganu <urwithsugh...@gmail.com>
Cc: Albert Aribaud <albert.u.b...@aribaud.net>
---
arch/arm/cpu/arm926ejs/start.S | 10 +++++++---
1 files changed, 7 insertions(+), 3 deletions(-)
diff --git a/arch/arm/cpu/arm926ejs/start.S b/arch/arm/cpu/arm926ejs/start.S
index 6a09c02..112f708 100644
--- a/arch/arm/cpu/arm926ejs/start.S
+++ b/arch/arm/cpu/arm926ejs/start.S
@@ -355,17 +355,21 @@ _dynsym_start_ofs:
*/
cpu_init_crit:
/*
- * flush v4 I/D caches
+ * flush D cache before disabling it
*/
mov r0, #0
- mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
+flush_dcache:
+ mrc p15, 0, r15, c7, c10, 3
+ bne flush_dcache
+
+ mov r0, #0
mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
/*
* disable MMU stuff and caches
*/
mrc p15, 0, r0, c1, c0, 0
- bic r0, r0, #0x00002300 /* clear bits 13, 9:8 (--V- --RS) */
+ bic r0, r0, #0x00000300 /* clear bits 13, 9:8 ( --RS) */
bic r0, r0, #0x00000087 /* clear bits 7, 2:0 (B--- -CAM) */
orr r0, r0, #0x00000002 /* set bit 2 (A) Align */
orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */
--
1.7.5.4
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