For tegra we want to enable the cache for the LCD. This is easier if we can avoid using L2 page tages, so align the LCD to a section boundary.
Signed-off-by: Simon Glass <s...@chromium.org> --- include/configs/tegra2-common.h | 1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/include/configs/tegra2-common.h b/include/configs/tegra2-common.h index 97ac6cd..ff4d90d 100644 --- a/include/configs/tegra2-common.h +++ b/include/configs/tegra2-common.h @@ -44,6 +44,7 @@ #define CONFIG_SYS_CACHELINE_SIZE 32 #define CONFIG_ARCH_CPU_INIT /* Fire up the A9 core */ +#define CONFIG_ALIGN_LCD_TO_SECTION /* Align LCD to 1MB boundary */ #include <asm/arch/tegra2.h> /* get chip and board defs */ -- 1.7.7.3 _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
