The patch renames the macro PHY_RESET_VAL to LPDDR3PHY_CTRL_PHY_RESET for
clarity and also fixes a minor typo error to make the bit description similar
to as described in the Exynos user manual.

Signed-off-by: Hatim Ali <[email protected]>

diff --git a/board/samsung/smdk5250/dmc_init_lpddr2.c 
b/board/samsung/smdk5250/dmc_init_lpddr2.c
index 7881074..846469e 100644
--- a/board/samsung/smdk5250/dmc_init_lpddr2.c
+++ b/board/samsung/smdk5250/dmc_init_lpddr2.c
@@ -53,7 +53,7 @@ static void reset_phy_ctrl(void)
 {
        struct exynos5_clock *clk = (struct exynos5_clock *)EXYNOS5_CLOCK_BASE;
 
-       writel(PHY_RESET_VAL, &clk->lpddr3phy_ctrl);
+       writel(LPDDR3PHY_CTRL_PHY_RESET_OFF, &clk->lpddr3phy_ctrl);
        sdelay(0x10000);
 }
 
@@ -246,9 +246,9 @@ static void config_rdlvl(struct exynos5_dmc *dmc,
        /*
         * Set ctrl_gateadj, ctrl_readadj
         * ctrl_gateduradj, rdlvl_pass_adj
-        * rdlvl_rddataPadj
+        * rdlvl_rddata_adj
         */
-       val = SET_RDLVL_RDDATAPADJ;
+       val = SET_RDLVL_RDDATA_ADJ;
        writel(val, &phy0_ctrl->phy_con1);
        writel(val, &phy1_ctrl->phy_con1);
 
diff --git a/board/samsung/smdk5250/setup.h b/board/samsung/smdk5250/setup.h
index 1276fd3..cf572ac 100644
--- a/board/samsung/smdk5250/setup.h
+++ b/board/samsung/smdk5250/setup.h
@@ -353,7 +353,8 @@
 /* (Memory Interleaving Size = 1 << IV_SIZE) */
 #define CONFIG_IV_SIZE         0x07
 
-#define PHY_RESET_VAL  (0 << 0)
+#define LPDDR3PHY_CTRL_PHY_RESET       (1 << 0)
+#define LPDDR3PHY_CTRL_PHY_RESET_OFF   (0 << 0)
 
 /*ZQ Configurations */
 #define PHY_CON16_RESET_VAL    0x08000304
@@ -397,9 +398,9 @@
 #define SET_CTRL_DDR_MODE(x, y)        (x = (x & ~(0x3 << 11)) | y << 11)
 
 #define PHY_CON1_RESET_VAL     0x9210100
-#define RDLVL_RDDATAPADJ       0x1
-#define SET_RDLVL_RDDATAPADJ   ((PHY_CON1_RESET_VAL & ~(0xFFFF << 0))\
-                                       | RDLVL_RDDATAPADJ << 0)
+#define RDLVL_RDDATA_ADJ       0x1
+#define SET_RDLVL_RDDATA_ADJ   ((PHY_CON1_RESET_VAL & ~(0xFFFF << 0)) \
+                                       | RDLVL_RDDATA_ADJ << 0)
 
 #define PHY_CON2_RESET_VAL     0x00010004
 #define RDLVL_EN               (1 << 25)
-- 
1.7.2.3

_______________________________________________
U-Boot mailing list
[email protected]
http://lists.denx.de/mailman/listinfo/u-boot

Reply via email to