This patch requires Stefano's driver for MX5/MX6.
http://lists.denx.de/pipermail/u-boot/2012-February/118530.html
Signed-off-by: Eric Nelson <[email protected]>
---
arch/arm/include/asm/arch-mx6/imx-regs.h | 11 +++++
board/freescale/mx6qsabrelite/mx6qsabrelite.c | 54 +++++++++++++++++++++++++
include/configs/mx6qsabrelite.h | 13 ++++++
3 files changed, 78 insertions(+), 0 deletions(-)
diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h
b/arch/arm/include/asm/arch-mx6/imx-regs.h
index 3e5c4c2..2441434 100644
--- a/arch/arm/include/asm/arch-mx6/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx6/imx-regs.h
@@ -165,6 +165,17 @@
#define IP2APB_USBPHY1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x78000)
#define IP2APB_USBPHY2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x7C000)
+/*
+ * ANATOP register definitions
+ */
+#define ANATOP_PLL_LOCK 0x80000000
+#define ANATOP_PLL_ENABLE_MASK 0x00002000
+#define ANATOP_PLL_BYPASS_MASK 0x00010000
+#define ANATOP_PLL_LOCK 0x80000000
+#define ANATOP_PLL_PWDN_MASK 0x00001000
+#define ANATOP_PLL_HOLD_RING_OFF_MASK 0x00000800
+#define ANATOP_SATA_CLK_ENABLE_MASK 0x00100000
+
#define CHIP_REV_1_0 0x10
#define IRAM_SIZE 0x00040000
#define IMX_IIM_BASE OCOTP_BASE_ADDR
diff --git a/board/freescale/mx6qsabrelite/mx6qsabrelite.c
b/board/freescale/mx6qsabrelite/mx6qsabrelite.c
index 2786482..e0ba6a4 100644
--- a/board/freescale/mx6qsabrelite/mx6qsabrelite.c
+++ b/board/freescale/mx6qsabrelite/mx6qsabrelite.c
@@ -273,10 +273,64 @@ int board_eth_init(bd_t *bis)
return 0;
}
+#ifdef CONFIG_CMD_SATA
+
+int setup_sata(void)
+{
+ u32 reg = 0;
+ s32 timeout = 100000;
+
+ /* Enable sata clock */
+ reg = readl(CCM_BASE_ADDR + 0x7c); /* CCGR5 */
+ reg |= 0x30;
+ writel(reg, CCM_BASE_ADDR + 0x7c);
+
+ /* Enable PLLs */
+ reg = readl(ANATOP_BASE_ADDR + 0xe0); /* ENET PLL */
+ reg &= ~ANATOP_PLL_PWDN_MASK;
+ writel(reg, ANATOP_BASE_ADDR + 0xe0);
+ reg |= ANATOP_PLL_ENABLE_MASK;
+ while (timeout--) {
+ if (readl(ANATOP_BASE_ADDR + 0xe0) & ANATOP_PLL_LOCK)
+ break;
+ }
+ if (timeout <= 0)
+ return -1;
+ reg &= ~ANATOP_PLL_BYPASS_MASK;
+ writel(reg, ANATOP_BASE_ADDR + 0xe0);
+ reg |= ANATOP_SATA_CLK_ENABLE_MASK;
+ writel(reg, ANATOP_BASE_ADDR + 0xe0);
+
+ /* Enable sata phy */
+ reg = readl(IOMUXC_BASE_ADDR + 0x34); /* GPR13 */
+
+ reg &= ~0x07ffffff;
+ /*
+ * rx_eq_val_0 = 5 [26:24] == 3.0 dB
+ * los_lvl = 0x12 [23:19] == SATA2m
+ * rx_dpll_mode_0 = 0x3 [18:16]
+ * speed = 1 [15] == 3Gpbs
+ * mpll_ss_en = 0x0 [14]
+ * tx_atten_0 = 0x4 [13:11]
+ * tx_boost_0 = 0x0 [10:7]
+ * tx_lvl = 0x11 [6:2] == 1.104 V
+ * tx_edgerate_0 == 0x0 [0:1]
+ * */
+ reg |= 0x0593a046;
+ writel(reg, IOMUXC_BASE_ADDR + 0x34);
+
+ return 0;
+}
+#endif
+
int board_early_init_f(void)
{
setup_iomux_uart();
+#ifdef CONFIG_CMD_SATA
+ setup_sata();
+#endif
+
return 0;
}
diff --git a/include/configs/mx6qsabrelite.h b/include/configs/mx6qsabrelite.h
index a5dae73..01c6887 100644
--- a/include/configs/mx6qsabrelite.h
+++ b/include/configs/mx6qsabrelite.h
@@ -69,6 +69,19 @@
#define CONFIG_CMD_FAT
#define CONFIG_DOS_PARTITION
+#define CONFIG_CMD_SATA
+/*
+ * SATA Configs
+ */
+#ifdef CONFIG_CMD_SATA
+#define CONFIG_DWC_AHSATA
+#define CONFIG_SYS_SATA_MAX_DEVICE 1
+#define CONFIG_DWC_AHSATA_PORT_ID 0
+#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR
+#define CONFIG_LBA48
+#define CONFIG_LIBATA
+#endif
+
#define CONFIG_CMD_PING
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_MII
--
1.7.9
_______________________________________________
U-Boot mailing list
[email protected]
http://lists.denx.de/mailman/listinfo/u-boot
