The DMA mode didn't properly configure the DMA_ENABLE bit in CTRL1.
Also, it was using SSP0 DMA channel for all SSP devices.
Signed-off-by: Marek Vasut <ma...@denx.de>
Cc: Wolfgang Denk <w...@denx.de>
Cc: Stefano Babic <sba...@denx.de>
Cc: Fabio Estevam <feste...@freescale.com>
Cc: Andy Fleming <aflem...@freescale.com>
---
drivers/mmc/mxsmmc.c | 10 ++++++++--
1 file changed, 8 insertions(+), 2 deletions(-)
NOTE: This series is for -next!
diff --git a/drivers/mmc/mxsmmc.c b/drivers/mmc/mxsmmc.c
index 4187a94..a637db3 100644
--- a/drivers/mmc/mxsmmc.c
+++ b/drivers/mmc/mxsmmc.c
@@ -79,6 +79,7 @@ mxsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct
mmc_data *data)
uint32_t *data_ptr;
#else
uint32_t cache_data_count;
+ int dmach;
#endif
debug("MMC%d: CMD%d\n", mmc->block_dev.dev, cmd->cmdidx);
@@ -201,6 +202,8 @@ mxsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
struct mmc_data *data)
timeout = MXSMMC_MAX_TIMEOUT;
#ifdef CONFIG_MXS_MMC_DMA
+ writel(SSP_CTRL1_DMA_ENABLE, &ssp_regs->hw_ssp_ctrl1_set);
+
if (data_count % ARCH_DMA_MINALIGN)
cache_data_count = roundup(data_count, ARCH_DMA_MINALIGN);
else
@@ -222,8 +225,9 @@ mxsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
struct mmc_data *data)
(data_count << MXS_DMA_DESC_BYTES_OFFSET);
- mxs_dma_desc_append(MXS_DMA_CHANNEL_AHB_APBH_SSP0, priv->desc);
- if (mxs_dma_go(MXS_DMA_CHANNEL_AHB_APBH_SSP0)) {
+ dmach = MXS_DMA_CHANNEL_AHB_APBH_SSP0 + priv->id;
+ mxs_dma_desc_append(dmach, priv->desc);
+ if (mxs_dma_go(dmach)) {
printf("MMC%d: DMA transfer failed\n", mmc->block_dev.dev);
return COMM_ERR;
}
@@ -234,6 +238,8 @@ mxsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
struct mmc_data *data)
(uint32_t)(priv->desc->cmd.address + cache_data_count));
}
#else
+ writel(SSP_CTRL1_DMA_ENABLE, &ssp_regs->hw_ssp_ctrl1_clr);
+
if (data->flags & MMC_DATA_READ) {
data_ptr = (uint32_t *)data->dest;
while (data_count && --timeout) {
--
1.7.10
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