We were not comparing the SVRs properly previously. This comparison
will properly shift the SVR and mask off the E bit
This fixes the boot output to show the correct DDR bus width:
512 MiB (DDR3, 16-bit, CL=5, ECC off)
instead of
512 MiB (DDR3, 32-bit, CL=5, ECC off)
Signed-off-by: Matthew McClintock <m...@freescale.com>
---
nand_spl/board/freescale/p1010rdb/nand_boot.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/nand_spl/board/freescale/p1010rdb/nand_boot.c
b/nand_spl/board/freescale/p1010rdb/nand_boot.c
index 1f89ab5..f5294d0 100644
--- a/nand_spl/board/freescale/p1010rdb/nand_boot.c
+++ b/nand_spl/board/freescale/p1010rdb/nand_boot.c
@@ -35,7 +35,8 @@ unsigned long ddr_freq_mhz;
void sdram_init(void)
{
ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC85xx_DDR_ADDR;
- u32 svr = mfspr(SPRN_SVR);
+ /* mask off E bit */
+ u32 svr = SVR_SOC_VER(mfspr(SPRN_SVR));
out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL | SDRAM_CFG_32_BE);
out_be32(&ddr->cs0_bnds, CONFIG_SYS_DDR_CS0_BNDS);
--
1.7.9.7
_______________________________________________
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
