The QCSP registers are at offset 0x1000 for SoCs with QMan v3.
Signed-off-by: York Sun <york...@freescale.com>
---
arch/powerpc/include/asm/immap_85xx.h | 19 ++++++++++++++++++-
1 files changed, 18 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/include/asm/immap_85xx.h
b/arch/powerpc/include/asm/immap_85xx.h
index 15d2db4..20e6915 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -2573,13 +2573,18 @@ typedef struct ccsr_sec {
#endif
typedef struct ccsr_qman {
+#ifdef CONFIG_SYS_FSL_QMAN_V3
+ /* T4240, PSC9164 */
+ u8 res0[0x200];
+#else
+ /* P4080, SC4080, P3041, P5020, P1023, SC1023 */
struct {
u32 qcsp_lio_cfg; /* 0x0 - SW Portal n LIO cfg */
u32 qcsp_io_cfg; /* 0x4 - SW Portal n IO cfg */
u32 res;
u32 qcsp_dd_cfg; /* 0xc - SW Portal n Dynamic Debug cfg
*/
} qcsp[32];
-
+#endif
/* Not actually reserved, but irrelevant to u-boot */
u8 res[0xbf8 - 0x200];
u32 ip_rev_1;
@@ -2604,6 +2609,18 @@ typedef struct ccsr_qman {
u32 ci_rlm_cfg; /* Initiator Read Latency Monitor Cfg */
u32 ci_rlm_avg; /* Initiator Read Latency Monitor Avg */
u8 res7[0x2e8];
+#ifdef CONFIG_SYS_FSL_QMAN_V3
+ /*
+ * T4240 50 software portals
+ * PSC9164 25 software portals
+ */
+ struct {
+ u32 qcsp_lio_cfg; /* 0x0 - SW Portal n LIO cfg */
+ u32 qcsp_io_cfg; /* 0x4 - SW Portal n IO cfg */
+ u32 res;
+ u32 qcsp_dd_cfg; /* 0xc - SW Portal n Dynamic Debug cfg
*/
+ } qcsp[50];
+#endif
} ccsr_qman_t;
typedef struct ccsr_bman {
--
1.7.0.4
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