On 22/08/2012 21:25, Matt Sealey wrote:
> PCBID pads seem to need time to settle due to external pulldowns, otherwise
> we are reading floating GPIO pins with implicit pad pullups and get the wrong
> data. However we can't "wait" at the time we need them before relocation,
> since timers are not available. The time taken to get from DCD to the code
> requiring the pads set seems to be more than long enough (even with caches
> enabled).
> 
> We have space in the DCD due to the DDR settings changes to configure all
> the pad settings we need for this, plus the LED pad settings too which
> reduces the amount of code required later on.
> 
> Signed-off-by: Matt Sealey <[email protected]>
> ---
>  board/genesi/mx51_efikamx/imximage_mx.cfg |   10 ++++++++++
>  1 file changed, 10 insertions(+)
> 
> diff --git a/board/genesi/mx51_efikamx/imximage_mx.cfg 
> b/board/genesi/mx51_efikamx/imximage_mx.cfg
> index ea6b271..38fa760 100644
> --- a/board/genesi/mx51_efikamx/imximage_mx.cfg
> +++ b/board/genesi/mx51_efikamx/imximage_mx.cfg
> @@ -45,6 +45,16 @@ BOOT_FROM  spi
>  #    Address   absolute address of the register
>  #    value     value to be stored in the register
>  
> +# Essential GPIO settings to be done as early as possible
> +# PCBIDn pad settings are all the defaults except #2 which needs HVE off
> +DATA 4 0x73fa8134 0x3                        # PCBID0 ALT3 GPIO 3_16
> +DATA 4 0x73fa8130 0x3                        # PCBID1 ALT3 GPIO 3_17
> +DATA 4 0x73fa8128 0x3                        # PCBID2 ALT3 GPIO 3_11
> +DATA 4 0x73fa8504 0xe4                       # PCBID2 PAD ~HVE
> +DATA 4 0x73fa8198 0x3                        # LED0 ALT3 GPIO 3_13
> +DATA 4 0x73fa81c4 0x3                        # LED1 ALT3 GPIO 3_14
> +DATA 4 0x73fa81c8 0x3                        # LED2 ALT3 GPIO 3_15
> +
>  # DDR bus IOMUX PAD settings
>  DATA 4 0x73fa850c 0x20c5             # SDODT1
>  DATA 4 0x73fa8510 0x20c5             # SDODT0
> 

Acked-by: Stefano Babic <[email protected]>

Best regards,
Stefano Babic

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