On 10/08/2012 12:44:30 PM, York Sun wrote:
Move spin table to cached memory to comply with ePAPR v1.1.
Load R3 with 64-bit value if CONFIG_SYS_PPC64 is defined.
'M' bit is set for DDR TLB to maintain cache coherence.
See details in doc/README.mpc85xx-spin-table.
Signed-off-by: York Sun <york...@freescale.com>
---
README | 6 +
arch/powerpc/cpu/mpc85xx/fdt.c | 13 ++-
arch/powerpc/cpu/mpc85xx/mp.c | 61 +++++-----
arch/powerpc/cpu/mpc85xx/mp.h | 5 +-
arch/powerpc/cpu/mpc85xx/release.S | 179
+++++++++++++++++------------
arch/powerpc/cpu/mpc85xx/tlb.c | 2 +-
arch/powerpc/include/asm/config_mpc85xx.h | 3 +
doc/README.mpc85xx-spin-table | 26 +++++
8 files changed, 183 insertions(+), 112 deletions(-)
create mode 100644 doc/README.mpc85xx-spin-table
As we discussed internally, this patch needs to be RFC until changes go
into Linux to be compatible with a cacheable spin table.
-Scott
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