Hi Stephen, On Tue, Nov 6, 2012 at 1:27 PM, Stephen Warren <swar...@wwwdotorg.org> wrote: > From: Stephen Warren <swar...@nvidia.com> > > Tegra's MMC driver does DMA, and hence needs cache-aligned buffers. In > some cases (e.g. user load commands) this cannot be guaranteed by callers > of the MMC APIs. To solve this, modify the Tegra MMC driver to use the > new bounce_buffer_*() APIs. > > Note: Ideally, all U-Boot code will always provide address- and size- > aligned buffers, so a bounce buffer will only ever be needed for user- > supplied buffers (e.g. load commands). Ensuring this removes the need > for performance-sucking bounce buffer cache management and memcpy()s. > The one known exception at present is the SCR buffer in sd_change_freq(), > which is only 8 bytes long. Solving this requires enhancing struct > mmc_data to know the difference between buffer size and transferred data > size, or forcing all callers of mmc_send_cmd() to have allocated buffers > using ALLOC_CACHE_ALIGN_BUFFER(), which while true in this case, is not > enforced in any way at present, and so cannot be assumed by the core MMC > code. > > Signed-off-by: Stephen Warren <swar...@nvidia.com>
Tested on Seaboard, loading a kernel from ext2 partition. Acked-by: Simon Glass <s...@chromium.org> Tested-by: Simon Glass <s...@chromium.org> It's really nice to clean up the cache code as well, very slick. Regards, Simon _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
