From: Dinesh Maniyam <[email protected]> Reserve the upper half of DRAM for image headers in SPL on Arria10. This allows SPL to load the fitImage header, parse it, extract the FPGA core bitstream section from it, and program the FPGA.
Compute the buffer from gd->ram_base + gd->ram_size / 2, honor the offset argument, bounds-check against the reserved region, and return a 64-byte-aligned address. Signed-off-by: Tien Fong Chee <[email protected]> Signed-off-by: Dinesh Maniyam <[email protected]> --- arch/arm/mach-socfpga/spl_a10.c | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/arch/arm/mach-socfpga/spl_a10.c b/arch/arm/mach-socfpga/spl_a10.c index c20376f7f8e..a0729ece4b4 100644 --- a/arch/arm/mach-socfpga/spl_a10.c +++ b/arch/arm/mach-socfpga/spl_a10.c @@ -284,3 +284,35 @@ void spl_board_prepare_for_boot(void) writel(FSBL_IMAGE_IS_VALID, socfpga_get_sysmgr_addr() + SYSMGR_A10_ROMCODE_INITSWSTATE); } + +#if CONFIG_IS_ENABLED(LOAD_FIT) && CONFIG_IS_ENABLED(SPI_LOAD) +struct legacy_img_hdr *spl_get_load_buffer(ssize_t offset, size_t size) +{ + uintptr_t hdr_base, addr; + size_t hdr_size; + + if (offset < 0) + return NULL; + + /* Need DRAM initialized and sized */ + if (!gd->ram_size) + return NULL; + + /* + * Reserve the upper half of DRAM for FIT/uImage header parsing so + * the buffer scales with DDR size and stays clear of early SPL use + * of low memory. + */ + hdr_base = gd->ram_base + gd->ram_size / 2; + hdr_size = gd->ram_size / 2; + + if (size > hdr_size || (size_t)offset > hdr_size - size) + return NULL; + + addr = ALIGN(hdr_base + (size_t)offset, 64); + if (addr < hdr_base || addr - hdr_base + size > hdr_size) + return NULL; + + return (struct legacy_img_hdr *)addr; +} +#endif -- 2.43.7
