From: Dinesh Maniyam <[email protected]> Program SECURE_TRANS_REG when CONFIG_SPL_MMC is enabled so an ATF image loaded from MMC can access the secure DDR region reserved for ATF.
Add the SECURE_TRANS_* register defines to firewall.h for the System Manager secure-transaction register used by this write. Signed-off-by: Dinesh Maniyam <[email protected]> --- Changes in v2: - Rename subject to arm: socfpga: spl_agilex5: ... - Capitalize MMC and fix comment grammar - Remove stray closing brace after writel - Add SECURE_TRANS_* / NON_SECURE_ACCESS defines to firewall.h and include it History: -------- [v1] https://patchwork.ozlabs.org/project/uboot/patch/[email protected]/ arch/arm/mach-socfpga/include/mach/firewall.h | 9 +++++++++ arch/arm/mach-socfpga/spl_agilex5.c | 8 ++++++++ 2 files changed, 17 insertions(+) diff --git a/arch/arm/mach-socfpga/include/mach/firewall.h b/arch/arm/mach-socfpga/include/mach/firewall.h index b47b577ae75..ca435869c8f 100644 --- a/arch/arm/mach-socfpga/include/mach/firewall.h +++ b/arch/arm/mach-socfpga/include/mach/firewall.h @@ -149,6 +149,15 @@ struct socfpga_firwall_l4_sys { writel(data, SOCFPGA_FW_MPU_DDR_SCR_ADDRESS + (reg)) #endif +/* Secure Transaction Register */ +#define SECURE_TRANS_OFFS 0x190 +#define SECURE_TRANS_REG SOCFPGA_SYSMGR_ADDRESS +\ + SECURE_TRANS_OFFS +#define SECURE_TRANS_RESET 0x0 +#define SECURE_TRANS_SET 0x33 + +#define NON_SECURE_ACCESS 0x0 + void firewall_setup(void); #endif /* _FIREWALL_H_ */ diff --git a/arch/arm/mach-socfpga/spl_agilex5.c b/arch/arm/mach-socfpga/spl_agilex5.c index 2c3e40b664a..2c58aa5b22e 100644 --- a/arch/arm/mach-socfpga/spl_agilex5.c +++ b/arch/arm/mach-socfpga/spl_agilex5.c @@ -11,6 +11,7 @@ #include <spl.h> #include <asm/arch/base_addr_soc64.h> #include <asm/arch/clock_manager.h> +#include <asm/arch/firewall.h> #include <asm/arch/mailbox_s10.h> #include <asm/arch/misc.h> #include <asm/arch/reset_manager.h> @@ -107,6 +108,13 @@ void board_init_f(ulong dummy) } } + /* + * Set secure transaction for MMC, so an ATF image loaded from MMC + * can be loaded to the secure region reserved for ATF in DDR. + */ + if (IS_ENABLED(CONFIG_SPL_MMC)) + writel(SECURE_TRANS_SET, SECURE_TRANS_REG); + if (IS_ENABLED(CONFIG_CADENCE_QSPI)) mbox_qspi_open(); -- 2.43.7
