From: Dinesh Maniyam <[email protected]> By using the handoff COMBOPHY selection data [BIT 16], we can determine whether the combophy used for SDMMC or NAND. The DFISEL configured for SDMMC if the handoff COMBOPHY sel [BIT 16] selected for SDMMC. This ensures that the appropriate PHY interface is enabled during early boot based on handoff configuration.
Signed-off-by: Dinesh Maniyam <[email protected]> --- Changes in v2: - Drop unused asm/arch/firewall.h include - Use fixed-size handoff_table[SOC64_HANDOFF_PERI_LEN] (no VLA) - Pass SOC64_HANDOFF_PERI_LEN directly to socfpga_handoff_read() - Fix comment to describe COMBOPHY/DFISEL selection from PERI handoff - Include asm/arch/handoff_soc64.h for handoff symbols History: -------- [v1] https://patchwork.ozlabs.org/project/uboot/patch/[email protected]/ .../mach-socfpga/include/mach/handoff_soc64.h | 1 + .../include/mach/system_manager_soc64.h | 1 + drivers/clk/altera/clk-agilex5.c | 16 ++++++++++++++++ 3 files changed, 18 insertions(+) diff --git a/arch/arm/mach-socfpga/include/mach/handoff_soc64.h b/arch/arm/mach-socfpga/include/mach/handoff_soc64.h index ae5af1f0100..e291d000907 100644 --- a/arch/arm/mach-socfpga/include/mach/handoff_soc64.h +++ b/arch/arm/mach-socfpga/include/mach/handoff_soc64.h @@ -81,6 +81,7 @@ #define SOC64_HANDOFF_PERI_LEN 1 #define SOC64_HANDOFF_SDRAM (SOC64_HANDOFF_BASE + 0x634) #define SOC64_HANDOFF_SDRAM_LEN 5 +#define SOC64_HANDOFF_COMBOPHY_SEL_MASK BIT(16) #endif #if IS_ENABLED(CONFIG_ARCH_SOCFPGA_STRATIX10) diff --git a/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h b/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h index 8be98d0ee46..ce780da76d9 100644 --- a/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h +++ b/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h @@ -18,6 +18,7 @@ void populate_sysmgr_pinmux(void); #define SYSMGR_SOC64_MPU_STATUS 0x10 #define SYSMGR_SOC64_COMBOPHY_DFISEL 0xfc #define SYSMGR_SOC64_COMBOPHY_DFISEL_SDMMC 0x1 +#define SYSMGR_SOC64_COMBOPHY_DFISEL_NAND 0x0 #define SYSMGR_SOC64_NANDGRP_L3MASTER 0x34 #define SYSMGR_SOC64_USB0_L3MASTER 0x38 #define SYSMGR_SOC64_USB1_L3MASTER 0x3c diff --git a/drivers/clk/altera/clk-agilex5.c b/drivers/clk/altera/clk-agilex5.c index 92b91a9dfc8..a100be32c94 100644 --- a/drivers/clk/altera/clk-agilex5.c +++ b/drivers/clk/altera/clk-agilex5.c @@ -21,6 +21,9 @@ #include <linux/string.h> #include <linux/types.h> #include <asm/arch/clock_manager.h> +#include <asm/arch/handoff_soc64.h> +#include <asm/arch/system_manager.h> +#include <asm/arch/system_manager_soc64.h> #include <dt-bindings/clock/agilex5-clock.h> #include <wait_bit.h> #include <clk-uclass.h> @@ -241,10 +244,15 @@ static void clk_basic_init(struct udevice *dev, struct socfpga_clk_plat *plat = dev_get_plat(dev); u32 vcocalib; uintptr_t base_addr = (uintptr_t)plat->regs; + u32 handoff_table[SOC64_HANDOFF_PERI_LEN]; if (!cfg) return; + /* Read PERI handoff for COMBOPHY select (DFISEL SDMMC vs NAND) */ + socfpga_handoff_read((void *)SOC64_HANDOFF_PERI, handoff_table, + SOC64_HANDOFF_PERI_LEN); + if (IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5_EMU)) { /* Take both PLL out of reset and power up */ CM_REG_SETBITS(plat, CLKMGR_MAINPLL_PLLGLOB, @@ -320,6 +328,14 @@ static void clk_basic_init(struct udevice *dev, CM_REG_WRITEL(plat, cfg->per_pll_emacctl, CLKMGR_PERPLL_EMACCTL); CM_REG_WRITEL(plat, cfg->per_pll_gpiodiv, CLKMGR_PERPLL_GPIODIV); + /* Combophy Selection for SDMMC */ + if (!(handoff_table[0] & SOC64_HANDOFF_COMBOPHY_SEL_MASK)) + writel(SYSMGR_SOC64_COMBOPHY_DFISEL_SDMMC, + socfpga_get_sysmgr_addr() + SYSMGR_SOC64_COMBOPHY_DFISEL); + else + writel(SYSMGR_SOC64_COMBOPHY_DFISEL_NAND, + socfpga_get_sysmgr_addr() + SYSMGR_SOC64_COMBOPHY_DFISEL); + /* Configure ping pong counters in control group */ CM_REG_WRITEL(plat, cfg->ctl_emacactr, CLKMGR_CTL_EMACACTR); CM_REG_WRITEL(plat, cfg->ctl_emacbctr, CLKMGR_CTL_EMACBCTR); -- 2.43.7
