The Genio 700 boot flow enters U-Boot SPL after an external DDR loader has initialized DRAM. SPL then needs the debug UART and eMMC controller, together with their clock, syscon, pinctrl and watchdog providers, to load the firmware FIT.
Signed-off-by: Julien Masson <[email protected]> Signed-off-by: Carlo Caione <[email protected]> --- arch/arm/dts/mt8390-genio-700-evk-u-boot.dtsi | 86 +++++++++++++++++++++++++++ 1 file changed, 86 insertions(+) diff --git a/arch/arm/dts/mt8390-genio-700-evk-u-boot.dtsi b/arch/arm/dts/mt8390-genio-700-evk-u-boot.dtsi index 586d15bf72e..2b392c866fb 100644 --- a/arch/arm/dts/mt8390-genio-700-evk-u-boot.dtsi +++ b/arch/arm/dts/mt8390-genio-700-evk-u-boot.dtsi @@ -5,3 +5,89 @@ */ #include "mt8188-u-boot.dtsi" + +&clk26m { + bootph-pre-ram; +}; + +&gic { + bootph-pre-ram; +}; + +&topckgen { + bootph-pre-ram; +}; + +&infracfg_ao { + bootph-pre-ram; +}; + +&pio { + bootph-pre-ram; +}; + +&watchdog { + bootph-pre-ram; +}; + +&apmixedsys { + bootph-pre-ram; +}; + +&uart0 { + bootph-pre-ram; +}; + +&mmc0 { + bootph-pre-ram; +}; + +/ { + memory@40000000 { + bootph-pre-ram; + }; +}; + +&mmc0_default_pins { + bootph-pre-ram; + + pins-clk { + bootph-pre-ram; + }; + + pins-cmd-dat { + bootph-pre-ram; + }; + + pins-rst { + bootph-pre-ram; + }; +}; + +&mmc0_uhs_pins { + bootph-pre-ram; + + pins-clk { + bootph-pre-ram; + }; + + pins-cmd-dat { + bootph-pre-ram; + }; + + pins-ds { + bootph-pre-ram; + }; + + pins-rst { + bootph-pre-ram; + }; +}; + +&uart0_pins { + bootph-pre-ram; + + pins { + bootph-pre-ram; + }; +}; -- 2.55.0
