Add support for SDCC1 (eMMC) clock on SA8775P platform. This patch depends on this series: https://patchwork.ozlabs.org/project/uboot/patch/[email protected]/
Signed-off-by: Balaji Selvanathan <[email protected]> --- Changes in v2: - Use GATE_CLK_POLLED instead of GATE_CLK --- drivers/clk/qcom/clock-sa8775p.c | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/drivers/clk/qcom/clock-sa8775p.c b/drivers/clk/qcom/clock-sa8775p.c index c36b480b300..586b4e1be32 100644 --- a/drivers/clk/qcom/clock-sa8775p.c +++ b/drivers/clk/qcom/clock-sa8775p.c @@ -74,6 +74,22 @@ static const struct freq_tbl ftbl_gcc_ufs_phy_unipro_core_clk_src[] = { { } }; +#define SDCC1_APPS_CLK_CMD_RCGR 0x20014 + +/* SDCC1 APPS clock frequency table */ +static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk_src[] = { + F(144000, CFG_CLK_SRC_CXO, 16, 3, 25), + F(400000, CFG_CLK_SRC_CXO, 12, 1, 4), + F(19200000, CFG_CLK_SRC_CXO, 1, 0, 0), + F(20000000, CFG_CLK_SRC_GPLL0_EVEN, 5, 1, 3), + F(25000000, CFG_CLK_SRC_GPLL0_EVEN, 12, 0, 0), + F(50000000, CFG_CLK_SRC_GPLL0_EVEN, 6, 0, 0), + F(100000000, CFG_CLK_SRC_GPLL0_EVEN, 3, 0, 0), + F(192000000, CFG_CLK_SRC_GPLL9, 4, 0, 0), + F(384000000, CFG_CLK_SRC_GPLL9, 2, 0, 0), + { } +}; + static ulong sa8775p_set_rate(struct clk *clk, ulong rate) { struct msm_clk_priv *priv = dev_get_priv(clk->dev); @@ -94,6 +110,7 @@ static ulong sa8775p_set_rate(struct clk *clk, ulong rate) 5, 0, 0, CFG_CLK_SRC_GPLL0, 8); clk_rcg_set_rate(priv->base, USB3_PRIM_PHY_AUX_CMD_RCGR, 0, 0); return rate; + case GCC_UFS_PHY_AXI_CLK: freq = qcom_find_freq(ftbl_gcc_ufs_phy_axi_clk_src, rate); clk_rcg_set_rate_mnd(priv->base, UFS_PHY_AXI_CLK_CMD_RCGR, @@ -112,6 +129,12 @@ static ulong sa8775p_set_rate(struct clk *clk, ulong rate) case GCC_UFS_PHY_PHY_AUX_CLK: clk_rcg_set_rate(priv->base, UFS_PHY_PHY_AUX_CLK_CMD_RCGR, 0, CFG_CLK_SRC_CXO); return 19200000; + + case GCC_SDCC1_APPS_CLK: + freq = qcom_find_freq(ftbl_gcc_sdcc1_apps_clk_src, rate); + clk_rcg_set_rate_mnd(priv->base, SDCC1_APPS_CLK_CMD_RCGR, + freq->pre_div, freq->m, freq->n, freq->src, 8); + return freq->freq; default: return 0; } @@ -169,6 +192,10 @@ static const struct gate_clk sa8775p_clks[] = { /* EDP reference clock (used by UFS PHY) */ GATE_CLK_POLLED(GCC_EDP_REF_CLKREF_EN, 0x97448, BIT(0), 0x97448), + + /* SDCC1 clocks */ + GATE_CLK_POLLED(GCC_SDCC1_AHB_CLK, 0x2000c, BIT(0), 0x2000c), + GATE_CLK_POLLED(GCC_SDCC1_APPS_CLK, 0x20004, BIT(0), 0x20004), }; static int sa8775p_enable(struct clk *clk) --- base-commit: 2b66f9cf0492b23ac27ca4523151e2bddbab3c4f change-id: 20260723-lemans_emmc-395deb5f4a67 Best regards, -- Balaji Selvanathan <[email protected]>
