Add firmware interface for UFS access but also keep IO interface when firmware is not enabled.
Signed-off-by: Michal Simek <[email protected]> --- Changes in v2: - also move prototypes to generic header arch/arm/mach-versal2/cpu.c | 24 ++++++ .../arm/mach-versal2/include/mach/sys_proto.h | 7 +- drivers/firmware/firmware-zynqmp.c | 79 +++++++++++++++++-- drivers/ufs/ufs-amd-versal2.c | 4 +- include/zynqmp_firmware.h | 13 +-- 5 files changed, 112 insertions(+), 15 deletions(-) diff --git a/arch/arm/mach-versal2/cpu.c b/arch/arm/mach-versal2/cpu.c index 6cc6592b0fc1..01efa7b79282 100644 --- a/arch/arm/mach-versal2/cpu.c +++ b/arch/arm/mach-versal2/cpu.c @@ -160,6 +160,30 @@ u8 __weak versal2_get_bootmode(void) return bootmode; } +int __weak zynqmp_pm_ufs_get_txrx_cfgrdy(u32 *value) +{ + *value = readl(PMXC_SLCR_BASE_ADDRESS + PMXC_TX_RX_CFG_RDY); + return 0; +} + +int __weak zynqmp_pm_ufs_sram_csr_read(u32 *value) +{ + *value = readl(PMXC_SLCR_BASE_ADDRESS + PMXC_SRAM_CSR); + return 0; +} + +int __weak zynqmp_pm_ufs_sram_csr_write(u32 *value) +{ + writel(*value, PMXC_SLCR_BASE_ADDRESS + PMXC_SRAM_CSR); + return 0; +} + +int __weak zynqmp_pm_ufs_cal_reg(u32 *value) +{ + *value = readl(PMXC_EFUSE_CACHE_BASE_ADDRESS + PMXC_UFS_CAL_1_OFFSET); + return 0; +} + void versal2_timer_setup(void) { u32 val; diff --git a/arch/arm/mach-versal2/include/mach/sys_proto.h b/arch/arm/mach-versal2/include/mach/sys_proto.h index b8d12d1dd3bb..c1dfd184d865 100644 --- a/arch/arm/mach-versal2/include/mach/sys_proto.h +++ b/arch/arm/mach-versal2/include/mach/sys_proto.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (C) 2021 - 2022, Xilinx, Inc. - * Copyright (C) 2022 - 2024, Advanced Micro Devices, Inc. + * Copyright (C) 2022 - 2026, Advanced Micro Devices, Inc. */ #ifndef _ASM_ARCH_SYS_PROTO_H @@ -22,4 +22,9 @@ u8 versal2_get_bootmode(void); /* EL3 clock/timer register setup, called from board_early_init_r() */ void versal2_timer_setup(void); +int zynqmp_pm_ufs_get_txrx_cfgrdy(u32 *value); +int zynqmp_pm_ufs_sram_csr_read(u32 *value); +int zynqmp_pm_ufs_sram_csr_write(u32 *value); +int zynqmp_pm_ufs_cal_reg(u32 *value); + #endif /* _ASM_ARCH_SYS_PROTO_H */ diff --git a/drivers/firmware/firmware-zynqmp.c b/drivers/firmware/firmware-zynqmp.c index 0783aa9a8ab7..2bdb1c4d9f89 100644 --- a/drivers/firmware/firmware-zynqmp.c +++ b/drivers/firmware/firmware-zynqmp.c @@ -177,26 +177,89 @@ unsigned int zynqmp_firmware_version(void) #if defined(CONFIG_ARCH_VERSAL2) int zynqmp_pm_ufs_get_txrx_cfgrdy(u32 *value) { - *value = readl(PMXC_SLCR_BASE_ADDRESS + PMXC_TX_RX_CFG_RDY); - return 0; + u32 ret_payload[PAYLOAD_ARG_CNT]; + int ret; + + if (!value) + return -EINVAL; + + ret = xilinx_pm_request(PM_IOCTL, PM_REGNODE_PMC_IOU_SLCR, + IOCTL_READ_REG, TXRX_CFGRDY_OFFSET, 0, 0, + 0, ret_payload); + if (ret) + return ret; + + *value = ret_payload[1]; + + return ret; } int zynqmp_pm_ufs_sram_csr_read(u32 *value) { - *value = readl(PMXC_SLCR_BASE_ADDRESS + PMXC_SRAM_CSR); - return 0; + u32 ret_payload[PAYLOAD_ARG_CNT]; + int ret; + + if (!value) + return -EINVAL; + + ret = xilinx_pm_request(PM_IOCTL, PM_REGNODE_PMC_IOU_SLCR, + IOCTL_READ_REG, SRAM_CSR_OFFSET, 0, 0, + 0, ret_payload); + if (ret) + return ret; + + *value = ret_payload[1]; + + return ret; } int zynqmp_pm_ufs_sram_csr_write(u32 *value) { - writel(*value, PMXC_SLCR_BASE_ADDRESS + PMXC_SRAM_CSR); - return 0; + int ret; + + if (!value) + return -EINVAL; + + ret = zynqmp_pm_is_function_supported(PM_IOCTL, IOCTL_MASK_WRITE_REG); + if (ret) { + printf("%s: IOCTL_MASK_WRITE_REG is not supported : %d\n" + , __func__, ret); + return 0; + } + + ret = xilinx_pm_request(PM_IOCTL, PM_REGNODE_PMC_IOU_SLCR, + IOCTL_MASK_WRITE_REG, SRAM_CSR_OFFSET, + GENMASK(2, 1), *value, 0, NULL); + if (ret) + return ret; + + return ret; } int zynqmp_pm_ufs_cal_reg(u32 *value) { - *value = readl(PMXC_EFUSE_CACHE_BASE_ADDRESS + PMXC_UFS_CAL_1_OFFSET); - return 0; + u32 ret_payload[PAYLOAD_ARG_CNT]; + int ret; + + if (!value) + return -EINVAL; + + ret = zynqmp_pm_is_function_supported(PM_IOCTL, IOCTL_READ_REG); + if (ret) { + printf("%s: IOCTL_READ_REG is not supported : %d\n" + , __func__, ret); + return 0; + } + + ret = xilinx_pm_request(PM_IOCTL, PM_REGNODE_EFUSE_CACHE, + IOCTL_READ_REG, UFS_CAL_1_OFFSET, 0, 0, + 0, ret_payload); + if (ret) + return ret; + + *value = ret_payload[1]; + + return ret; } #endif /* CONFIG_ARCH_VERSAL2 */ diff --git a/drivers/ufs/ufs-amd-versal2.c b/drivers/ufs/ufs-amd-versal2.c index 3369d32d924c..25af9dd63cca 100644 --- a/drivers/ufs/ufs-amd-versal2.c +++ b/drivers/ufs/ufs-amd-versal2.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright (C) 2024-2025 Advanced Micro Devices, Inc. + * Copyright (C) 2024-2026 Advanced Micro Devices, Inc. */ #include <clk.h> @@ -14,6 +14,8 @@ #include <linux/time.h> #include <reset.h> +#include <asm/arch/sys_proto.h> + #include "ufs.h" #include "ufshcd-dwc.h" #include "ufshci-dwc.h" diff --git a/include/zynqmp_firmware.h b/include/zynqmp_firmware.h index 0e545e3db1be..f753a67ac276 100644 --- a/include/zynqmp_firmware.h +++ b/include/zynqmp_firmware.h @@ -465,10 +465,6 @@ int zynqmp_mmio_read(const u32 address, u32 *value); int zynqmp_mmio_write(const u32 address, const u32 mask, const u32 value); int zynqmp_pm_feature(const u32 api_id); u32 zynqmp_pm_get_bootmode_reg(void); -int zynqmp_pm_ufs_get_txrx_cfgrdy(u32 *value); -int zynqmp_pm_ufs_sram_csr_read(u32 *value); -int zynqmp_pm_ufs_sram_csr_write(u32 *value); -int zynqmp_pm_ufs_cal_reg(u32 *value); u32 zynqmp_pm_get_pmc_multi_boot_reg(void); u32 zynqmp_pm_get_pmc_global_pggs_reg(u32 reg_addr); @@ -535,7 +531,14 @@ extern smc_call_handler_t __data smc_call_handler; #define PM_DEV_OSPI (0x1822402aU) -#define PM_REG_PGGS3 0x30004003 +#define PM_REGNODE_PMC_IOU_SLCR 0x30000002 +#define PM_REGNODE_EFUSE_CACHE 0x30000003 +#define PM_REG_PGGS3 0x30004003 + +#define SRAM_CSR_OFFSET 0x104C +#define TXRX_CFGRDY_OFFSET 0x1054 +#define UFS_CAL_1_OFFSET 0xBE8 + #define PMC_GLOBAL_PGGS3_REG_NODE 0x1824C005 #endif /* _ZYNQMP_FIRMWARE_H_ */ --- base-commit: 3a500867bf0b8527ee7e94c325ce876562fba6c8 branch: debian-sent3 -- 2.43.0
