On Fri, May 15, 2026 at 02:47:53PM +0200, Michal Simek wrote: > The Xilinx MicroBlaze V platform does not have an ACLINT (Advanced > Core Local Interruptor) hardware block. The timer functionality is > provided through a different mechanism. > > Exclude both RISCV_ACLINT and SPL_RISCV_ACLINT from being implied > for TARGET_XILINX_MBV while keeping the default behavior for other > generic RISC-V targets that do have ACLINT hardware. > > spl/u-boot-spl: all -1382 data -360 rodata -200 text -822 > > Signed-off-by: Michal Simek <[email protected]> > --- > > (no changes since v2) > > Changes in v2: > - Separate platform defconfig from core Kconfig > > configs/xilinx_mbv32_defconfig | 2 ++ > 1 file changed, 2 insertions(+)
Applied to u-boot-riscv/main, thanks. Reviewed-by: Leo Yu-Chi Liang <[email protected]> Best regards, Leo
