From: Alif Zakuan Yuslaimi <[email protected]> Add initial Agilex3 SoCDK board support based on the Agilex5 platform. Agilex3 reuses the Agilex5 SoC DTSI, U-Boot DTSI, and defconfig, with these board-level differences:
- Ethernet uses GMAC2 only with a Micrel KSZ90X1 PHY. Agilex5 enables GMAC0 and GMAC2 with a Marvell PHY - QSPI map is 12 MiB u-boot + 52 MiB root with U-Boot offset 0xa00000. Agilex5 uses 66 MiB + 190 MiB and offset 0x4000000 - QSPI boot script adds a fallback MTD layout for the smaller Agilex3 flash - MMC enables SDR104 (sdhci-caps-mask) in the board DT Signed-off-by: Alif Zakuan Yuslaimi <[email protected]> --- arch/arm/dts/Makefile | 1 + .../arm/dts/socfpga_agilex3_socdk-u-boot.dtsi | 179 ++++++++++++++ arch/arm/dts/socfpga_agilex3_socdk.dts | 222 ++++++++++++++++++ configs/socfpga_agilex3_defconfig | 8 + include/configs/socfpga_soc64_common.h | 22 +- 5 files changed, 426 insertions(+), 6 deletions(-) create mode 100644 arch/arm/dts/socfpga_agilex3_socdk-u-boot.dtsi create mode 100644 arch/arm/dts/socfpga_agilex3_socdk.dts create mode 100644 configs/socfpga_agilex3_defconfig diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 25234697e6a..90755277bab 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -415,6 +415,7 @@ dtb-$(CONFIG_AM43XX) += am437x-gp-evm.dtb am437x-sk-evm.dtb \ dtb-$(CONFIG_TARGET_THUNDERX_88XX) += thunderx-88xx.dtb dtb-$(CONFIG_ARCH_SOCFPGA) += \ + socfpga_agilex3_socdk.dtb \ socfpga_agilex5_socdk.dtb \ socfpga_agilex5_socdk_emmc.dtb \ socfpga_arria5_secu1.dtb \ diff --git a/arch/arm/dts/socfpga_agilex3_socdk-u-boot.dtsi b/arch/arm/dts/socfpga_agilex3_socdk-u-boot.dtsi new file mode 100644 index 00000000000..b14277d5b8d --- /dev/null +++ b/arch/arm/dts/socfpga_agilex3_socdk-u-boot.dtsi @@ -0,0 +1,179 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * U-Boot additions + * + * Copyright (C) 2026 Altera Corporation <www.altera.com> + */ + +#include "socfpga_agilex5-u-boot.dtsi" + +/{ + aliases { + spi0 = &qspi; + freeze_br0 = &freeze_controller; + }; + + soc { + freeze_controller: freeze_controller@0x20000450 { + compatible = "altr,freeze-bridge-controller"; + reg = <0x20000450 0x00000010>; + status = "disabled"; + }; + }; + + /* + * Both Memory base address and size default info is retrieved from HW setting. + * Reconfiguration / Overwrite these info can be done with examples below. + */ + + /* + * Example for memory size with 2GB: + * memory { + * reg = <0x0 0x80000000 0x0 0x80000000>; + * }; + */ + + /* + * Example for memory size with 8GB: + * memory { + * reg = <0x0 0x80000000 0x0 0x80000000>, + * <0x8 0x80000000 0x1 0x80000000>; + * }; + */ + + /* + * Example for memory size with 32GB: + * memory { + * reg = <0x0 0x80000000 0x0 0x80000000>, + * <0x8 0x80000000 0x7 0x80000000>; + * }; + */ + + /* + * Example for memory size with 512GB: + * memory { + * reg = <0x0 0x80000000 0x0 0x80000000>, + * <0x8 0x80000000 0x7 0x80000000>, + * <0x88 0x00000000 0x78 0x00000000>; + * }; + */ + + chosen { + stdout-path = "serial0:115200n8"; + u-boot,spl-boot-order = &mmc,&flash0,&nand,"/memory"; + }; +}; + +&service_reserved { + reg = <0x0 0x80000000 0x0 0x2000000>; +}; + +&flash0 { + compatible = "jedec,spi-nor"; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + bootph-all; + /delete-property/ cdns,read-delay; +}; + +&flash1 { + bootph-all; +}; + +&i3c0 { + bootph-all; +}; + +&i3c1 { + bootph-all; +}; + +&gpio1 { + portb: gpio-controller@0 { + bootph-all; + }; +}; + +&sd_emmc_power { + bootph-all; +}; + +&sd_io_1v8_reg { + gpios = <&portb 3 GPIO_ACTIVE_HIGH>; + bootph-all; +}; + +&mmc { + status = "okay"; + + no-mmc; + disable-wp; + cap-sd-highspeed; + vmmc-supply = <&sd_emmc_power>; + vqmmc-supply = <&sd_io_1v8_reg>; + max-frequency = <200000000>; + sdhci-caps = <0x00000000 0x0000c800>; + + /* SD card default speed (DS) and UHS-I SDR12 mode timing configuration */ + cdns,phy-dqs-timing-delay-sd-ds = <0x00780000>; + cdns,phy-gate-lpbk-ctrl-delay-sd-ds = <0x81a40040>; + cdns,phy-dll-slave-ctrl-sd-ds = <0x00a000fe>; + cdns,phy-dq-timing-delay-sd-ds = <0x28000001>; + + /* SD card high speed and UHS-I SDR25 mode timing configuration */ + cdns,phy-dqs-timing-delay-sd-hs = <0x780001>; + cdns,phy-gate-lpbk-ctrl-delay-sd-hs = <0x81a40040>; + cdns,phy-dq-timing-delay-sd-hs = <0x10000001>; + cdns,ctrl-hrs16-slave-ctrl-sd-hs = <0x101>; + cdns,ctrl-hrs07-timing-delay-sd-hs = <0xA0001>; + + /* SD card UHS-I SDR50 mode timing configuration */ + cdns,phy-dqs-timing-delay-emmc-sdr = <0x780004>; + cdns,phy-gate-lpbk-ctrl-delay-emmc-sdr = <0x80a40040>; + cdns,phy-dll-slave-ctrl-emmc-sdr = <0x4000004>; + cdns,phy-dq-timing-delay-emmc-sdr = <0x38000001>; + cdns,ctrl-hrs09-timing-delay-emmc-sdr = <0xf1c1800c>; + cdns,ctrl-hrs10-lpbk-ctrl-delay-emmc-sdr = <0x20000>; + cdns,ctrl-hrs16-slave-ctrl-emmc-sdr = <0x101>; + cdns,ctrl-hrs07-timing-delay-emmc-sdr = <0x90005>; + + /* SD card UHS-I SDR104 mode timing configuration */ + cdns,phy-dq-timing-delay-emmc-hs200 = <0x11000001>; + cdns,phy-dqs-timing-delay-emmc-hs200 = <0x780004>; + cdns,phy-dll-slave-ctrl-emmc-hs200 = <0x4d4d00>; + cdns,phy-gate-lpbk-ctrl-delay-emmc-hs200 = <0x81a40040>; + cdns,ctrl-hrs09-timing-delay-emmc-hs200 = <0xf1c18000>; + cdns,ctrl-hrs10-lpbk-ctrl-delay-emmc-hs200 = <0x90000>; + cdns,ctrl-hrs16-slave-ctrl-emmc-hs200 = <0x101>; + cdns,ctrl-hrs07-timing-delay-emmc-hs200 = <0xa0001>; + + bootph-all; +}; + +&qspi { + status = "okay"; +}; + +&nand { + bootph-all; +}; + +&timer0 { + bootph-all; +}; + +&timer1 { + bootph-all; +}; + +&timer2 { + bootph-all; +}; + +&timer3 { + bootph-all; +}; + +&watchdog0 { + bootph-all; +}; diff --git a/arch/arm/dts/socfpga_agilex3_socdk.dts b/arch/arm/dts/socfpga_agilex3_socdk.dts new file mode 100644 index 00000000000..2f331a30996 --- /dev/null +++ b/arch/arm/dts/socfpga_agilex3_socdk.dts @@ -0,0 +1,222 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2026 Altera Corporation <www.altera.com> + */ +#include "socfpga_agilex5.dtsi" + +/ { + model = "SoCFPGA Agilex3 SoCDK"; + + aliases { + serial0 = &uart0; + ethernet2 = &gmac2; + }; + + leds { + compatible = "gpio-leds"; + hps0 { + label = "hps_led0"; + gpios = <&portb 20 GPIO_ACTIVE_HIGH>; + }; + + hps1 { + label = "hps_led1"; + gpios = <&portb 19 GPIO_ACTIVE_HIGH>; + }; + + hps2 { + label = "hps_led2"; + gpios = <&portb 21 GPIO_ACTIVE_HIGH>; + }; + }; + + memory { + device_type = "memory"; + /* We expect the bootloader to fill in the reg */ + reg = <0 0 0 0>; + }; + + soc { + clocks { + osc1 { + clock-frequency = <25000000>; + }; + }; + }; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; +}; + +&i2c1 { + status = "okay"; +}; + +&i2c3 { + status = "okay"; +}; + +&i3c0 { + status = "okay"; +}; + +&i3c1 { + status = "okay"; +}; + +&mmc { + sd-uhs-sdr104; + sdhci-caps-mask = <0x00002000 0x0000ff00>; +}; + +&uart0 { + status = "okay"; +}; + +&usbphy0 { + status = "okay"; +}; + +&usb0 { + status = "okay"; + disable-over-current; +}; + +&usb31 { + status = "okay"; +}; + +&watchdog0 { + status = "okay"; +}; + +&watchdog1 { + status = "okay"; +}; + +&watchdog2 { + status = "okay"; +}; + +&watchdog3 { + status = "okay"; +}; + +&watchdog4 { + status = "okay"; +}; + +&timer0 { + status = "okay"; +}; + +&timer1 { + status = "okay"; +}; + +&timer2 { + status = "okay"; +}; + +&timer3 { + status = "okay"; +}; + +&spi0 { + status = "okay"; +}; + +&spi1 { + status = "okay"; +}; + +&nand { + status = "okay"; + + flash1: flash@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "u-boot"; + reg = <0 0x200000>; + }; + partition@200000 { + label = "root"; + reg = <0x200000 0x3fe00000>; + }; + }; +}; + +&qspi { + flash0: flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "mt25qu02g"; + reg = <0>; + spi-max-frequency = <100000000>; + + m25p,fast-read; + cdns,page-size = <256>; + cdns,block-size = <16>; + cdns,read-delay = <1>; + cdns,tshsl-ns = <50>; + cdns,tsd2d-ns = <50>; + cdns,tchsh-ns = <4>; + cdns,tslch-ns = <4>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + qspi_boot: partition@0 { + label = "u-boot"; + reg = <0x0 0x00c00000>; + }; + + root: partition@c00000 { + label = "root"; + reg = <0x00c00000 0x03400000>; + }; + }; + }; +}; + +&gmac2 { + status = "okay"; + phy-mode = "rgmii"; + phy-handle = <&emac2_phy0>; + max-frame-size = <9000>; + + mdio0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + emac2_phy0: ethernet-phy@0 { + reg = <0>; + rxc-skew-ps = <0>; + rxdv-skew-ps = <0>; + rxd0-skew-ps = <0>; + rxd1-skew-ps = <0>; + rxd2-skew-ps = <0>; + rxd3-skew-ps = <0>; + txc-skew-ps = <0>; + txen-skew-ps = <60>; + txd0-skew-ps = <60>; + txd1-skew-ps = <60>; + txd2-skew-ps = <60>; + txd3-skew-ps = <60>; + }; + }; +}; diff --git a/configs/socfpga_agilex3_defconfig b/configs/socfpga_agilex3_defconfig new file mode 100644 index 00000000000..9072312a015 --- /dev/null +++ b/configs/socfpga_agilex3_defconfig @@ -0,0 +1,8 @@ +#include <configs/socfpga_agilex5_defconfig> + +CONFIG_DEFAULT_DEVICE_TREE="socfpga_agilex3_socdk" +CONFIG_IDENT_STRING="socfpga_agilex3" +CONFIG_SYS_PROMPT="SOCFPGA_AGILEX3 # " +CONFIG_PHY_MICREL=y +CONFIG_PHY_MICREL_KSZ90X1=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x0a00000 diff --git a/include/configs/socfpga_soc64_common.h b/include/configs/socfpga_soc64_common.h index 4d333c63ad9..126f1e5cf97 100644 --- a/include/configs/socfpga_soc64_common.h +++ b/include/configs/socfpga_soc64_common.h @@ -77,12 +77,22 @@ "setenv mtdids 'nor0=nor0,nand0=nand.0' && " \ "setenv mtdparts 'mtdparts=nor0:66m(u-boot),190m(root); " \ "nand.0:2m(nand_uboot),500m(nand_root)' && " \ - "env select UBI; saveenv && " \ - "ubi part root && " \ - "if ubi part root && ubi readvol ${scriptaddr} script; " \ - "then echo QSPI: Running script from UBIFS; " \ - "elif sf read ${scriptaddr} ${qspiscriptaddr} ${scriptsize}; " \ - "then echo QSPI: Running script from JFFS2; fi; " \ + "env select UBI && " \ + "if ubi part root && ubi readvol ${scriptaddr} script; then " \ + "echo QSPI: Running script from UBIFS; " \ + "elif sf read ${scriptaddr} ${qspiscriptaddr} ${scriptsize}; then " \ + "echo QSPI: Running script from JFFS2; " \ + "source ${scriptaddr}; " \ + "echo QSPI: UBIFS/JFFS2 load failed, trying fallback layout...; " \ + "setenv mtdids 'nor0=nor0' && " \ + "setenv mtdparts 'mtdparts=nor0:12m(u-boot),52m(root)' && " \ + "env select UBI && " \ + "if ubi part root && ubi readvol ${scriptaddr} script; then " \ + "echo QSPI: Running script from UBIFS fallback; " \ + "elif sf read ${scriptaddr} ${qspiscriptaddr} ${scriptsize}; then " \ + "echo QSPI: Running script from JFFS2 fallback; " \ + "fi; " \ + "fi; " \ "echo QSPI: Trying to boot script at ${scriptaddr} && " \ "source ${scriptaddr}; " \ "echo QSPI: SCRIPT FAILED: continuing...; ubi detach;\0" -- 2.43.7
