From: Alif Zakuan Yuslaimi <[email protected]> Add dedicated device tree support for the Terasic DE-25 Nano board, which is based on Agilex5.
Following Terasic's Linux device tree for DE-25 Nano configuration in which UART and MMC mode differs from Altera SoCDK boards - enable UART1 instead of UARTT0 and using SDR50 instead of SDR104 mode for MMC. The device tree is also tweaked to enable the 16MB QSPI flash to store U-Boot image in a single partition for QSPI boot. New files added: - socfpga_agilex5_de25_nano.dts: Main device tree - socfpga_agilex5_de25_nano-u-boot.dtsi: U-Boot specific additions - configs/socfpga_agilex5_de25_nano_defconfig: Board configurations Build system integration: - Add build target in Makefile for DE25 Nano device tree binary file Signed-off-by: Will <[email protected]> Signed-off-by: Shi Lin Teoh <[email protected]> Signed-off-by: Alif Zakuan Yuslaimi <[email protected]> --- arch/arm/dts/Makefile | 1 + .../dts/socfpga_agilex5_de25_nano-u-boot.dtsi | 148 ++++++++++++++ arch/arm/dts/socfpga_agilex5_de25_nano.dts | 183 ++++++++++++++++++ configs/socfpga_agilex5_de25_nano_defconfig | 12 ++ 4 files changed, 344 insertions(+) create mode 100644 arch/arm/dts/socfpga_agilex5_de25_nano-u-boot.dtsi create mode 100644 arch/arm/dts/socfpga_agilex5_de25_nano.dts create mode 100644 configs/socfpga_agilex5_de25_nano_defconfig diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 25234697e6a..b59df585a92 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -415,6 +415,7 @@ dtb-$(CONFIG_AM43XX) += am437x-gp-evm.dtb am437x-sk-evm.dtb \ dtb-$(CONFIG_TARGET_THUNDERX_88XX) += thunderx-88xx.dtb dtb-$(CONFIG_ARCH_SOCFPGA) += \ + socfpga_agilex5_de25_nano.dtb \ socfpga_agilex5_socdk.dtb \ socfpga_agilex5_socdk_emmc.dtb \ socfpga_arria5_secu1.dtb \ diff --git a/arch/arm/dts/socfpga_agilex5_de25_nano-u-boot.dtsi b/arch/arm/dts/socfpga_agilex5_de25_nano-u-boot.dtsi new file mode 100644 index 00000000000..8e71a7c426a --- /dev/null +++ b/arch/arm/dts/socfpga_agilex5_de25_nano-u-boot.dtsi @@ -0,0 +1,148 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * U-Boot additions + * + * Copyright (C) 2026 Altera Corporation <www.altera.com> + */ + +#include "socfpga_agilex5-u-boot.dtsi" + +/{ + aliases { + spi0 = &qspi; + freeze_br0 = &freeze_controller; + }; + + soc { + freeze_controller: freeze_controller@0x20000450 { + compatible = "altr,freeze-bridge-controller"; + reg = <0x20000450 0x00000010>; + status = "disabled"; + }; + }; + + chosen { + stdout-path = "serial0:115200n8"; + u-boot,spl-boot-order = &mmc,&flash0,&nand,"/memory"; + }; +}; + +&flash0 { + compatible = "jedec,spi-nor"; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + bootph-all; + /delete-property/ cdns,read-delay; +}; + +&flash1 { + bootph-all; +}; + +&i3c0 { + bootph-all; +}; + +&i3c1 { + bootph-all; +}; + +&gpio1 { + portb: gpio-controller@0 { + bootph-all; + }; +}; + +&sd_emmc_power { + bootph-all; +}; + +&sd_io_1v8_reg { + gpios = <&portb 3 GPIO_ACTIVE_HIGH>; + bootph-all; +}; + +&mmc { + status = "okay"; + disable-wp; + cap-sd-highspeed; + no-mmc; + vmmc-supply = <&sd_emmc_power>; + vqmmc-supply = <&sd_io_1v8_reg>; + max-frequency = <200000000>; + sdhci-caps = <0x00000000 0x0000c800>; + /* SD card default speed (DS) and UHS-I SDR12 mode timing configuration */ + cdns,phy-dqs-timing-delay-sd-ds = <0x00780000>; + cdns,phy-gate-lpbk-ctrl-delay-sd-ds = <0x81a40040>; + cdns,phy-dll-slave-ctrl-sd-ds = <0x00a000fe>; + cdns,phy-dq-timing-delay-sd-ds = <0x28000001>; + /* SD card high speed and UHS-I SDR25 mode timing configuration */ + cdns,phy-dqs-timing-delay-sd-hs = <0x780001>; + cdns,phy-gate-lpbk-ctrl-delay-sd-hs = <0x81a40040>; + cdns,phy-dq-timing-delay-sd-hs = <0x10000001>; + cdns,ctrl-hrs16-slave-ctrl-sd-hs = <0x101>; + cdns,ctrl-hrs07-timing-delay-sd-hs = <0xA0001>; + bootph-all; +}; + +&qspi { + status = "okay"; +}; + +&nand { + bootph-all; +}; + +&timer0 { + bootph-all; +}; + +&timer1 { + bootph-all; +}; + +&timer2 { + bootph-all; +}; + +&timer3 { + bootph-all; +}; + +&watchdog0 { + bootph-all; +}; + +&gmac0 { + status = "okay"; + phy-mode = "rgmii-id"; + phy-handle = <&emac0_phy0>; + + max-frame-size = <9000>; + + mdio0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwxgmac-mdio"; + emac0_phy0: ethernet-phy@0 { + reg = <1>; + }; + }; +}; + +&gmac2 { + status = "disabled"; + phy-mode = "rgmii-id"; + phy-handle = <&emac2_phy0>; + + max-frame-size = <9000>; + + mdio0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwxgmac-mdio"; + emac2_phy0: ethernet-phy@0 { + reg = <0>; + }; + }; +}; diff --git a/arch/arm/dts/socfpga_agilex5_de25_nano.dts b/arch/arm/dts/socfpga_agilex5_de25_nano.dts new file mode 100644 index 00000000000..c64b7d5525d --- /dev/null +++ b/arch/arm/dts/socfpga_agilex5_de25_nano.dts @@ -0,0 +1,183 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2026 Altera Corporation <www.altera.com> + */ +#include "socfpga_agilex5.dtsi" + +/ { + model = "SoCFPGA Agilex5 Terasic DE25-Nano"; + + aliases { + serial0 = &uart1; + ethernet0 = &gmac0; + }; + + leds { + compatible = "gpio-leds"; + hps0 { + label = "hps_led0"; + gpios = <&portb 20 GPIO_ACTIVE_HIGH>; + }; + + hps1 { + label = "hps_led1"; + gpios = <&portb 19 GPIO_ACTIVE_HIGH>; + }; + + hps2 { + label = "hps_led2"; + gpios = <&portb 21 GPIO_ACTIVE_HIGH>; + }; + }; + + memory { + device_type = "memory"; + /* We expect the bootloader to fill in the reg */ + reg = <0 0 0 0>; + }; + + soc { + clocks { + osc1 { + clock-frequency = <25000000>; + }; + }; + }; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; +}; + +&i2c1 { + status = "okay"; +}; + +&i2c3 { + status = "okay"; +}; + +&mmc { + status = "okay"; + sdhci-caps-mask = <0x00002007 0x0000ff00>; +}; + +&sd_emmc_power { + bootph-all; +}; + +&sd_io_1v8_reg { + gpios = <&portb 3 GPIO_ACTIVE_HIGH>; + bootph-all; +}; + +&uart1 { + status = "okay"; + bootph-all; +}; + +&usbphy0 { + status = "okay"; +}; + +&usb0 { + status = "okay"; + disable-over-current; +}; + +&usb31 { + status = "okay"; +}; + +&watchdog0 { + status = "okay"; +}; + +&watchdog1 { + status = "okay"; +}; + +&watchdog2 { + status = "okay"; +}; + +&watchdog3 { + status = "okay"; +}; + +&watchdog4 { + status = "okay"; +}; + +&timer0 { + status = "okay"; +}; + +&timer1 { + status = "okay"; +}; + +&timer2 { + status = "okay"; +}; + +&timer3 { + status = "okay"; +}; + +&qspi { + flash0: flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "mt25qu02g"; + reg = <0>; + spi-max-frequency = <100000000>; + + m25p,fast-read; + cdns,page-size = <256>; + cdns,block-size = <16>; + cdns,read-delay = <1>; + cdns,tshsl-ns = <50>; + cdns,tsd2d-ns = <50>; + cdns,tchsh-ns = <4>; + cdns,tslch-ns = <4>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + qspi_boot: partition@0 { + label = "u-boot"; + reg = <0x0 0x01000000>; + }; + }; + }; +}; + +&nand { + status = "disabled"; + + flash1: flash@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "u-boot"; + reg = <0 0x200000>; + }; + partition@200000 { + label = "root"; + reg = <0x200000 0x3fe00000>; + }; + }; +}; diff --git a/configs/socfpga_agilex5_de25_nano_defconfig b/configs/socfpga_agilex5_de25_nano_defconfig new file mode 100644 index 00000000000..88b616149b6 --- /dev/null +++ b/configs/socfpga_agilex5_de25_nano_defconfig @@ -0,0 +1,12 @@ +#include <configs/socfpga_agilex5_defconfig> + +CONFIG_DEFAULT_DEVICE_TREE="socfpga_agilex5_de25_nano" +CONFIG_TARGET_SOCFPGA_AGILEX5_DE25_NANO=y +CONFIG_MMC_SPEED_MODE_SET=y +# CONFIG_ISO_PARTITION is not set +# CONFIG_EFI_PARTITION is not set +# CONFIG_SPL_MMC_UHS_SUPPORT is not set +# CONFIG_MMC_UHS_SUPPORT is not set +# CONFIG_SPL_MMC_IO_VOLTAGE is not set +# CONFIG_MMC_IO_VOLTAGE is not set +CONFIG_SYS_SPI_U_BOOT_OFFS=0x0a00000 -- 2.43.7
