Hi TF, On 17/4/2026 12:00 pm, Chee, Tien Fong wrote: > Hi DInesh, > > > On 11/3/2026 1:03 pm, [email protected] wrote: >> From: Dinesh Maniyam <[email protected]> >> >> This is fitImage for programming peripheral RBF only in SPL, so that user >> has option to program core RBF in U-Boot proper. The advantage of >> programming core RBF in U-Boot proper especially for SDMMC boot the >> performance can be increased up to around 90%, because program core RBF > > > Please clarify what “~90%” is relative to (e.g. core programming time, > total SPL time, etc.).
Will drop the percentage entirely, this is qualitative rather than a quantified percentage. > >> in SPL hitting penalty on alignment issue in common FAT driver. >> >> Signed-off-by: Tien Fong Chee <[email protected]> >> Signed-off-by: Dinesh Maniyam <[email protected]> >> --- >> .../fit_spl_fpga_periph_only.its | 38 +++++++++++++++++++ >> configs/socfpga_arria10_defconfig | 2 +- >> include/configs/socfpga_common.h | 2 + >> 3 files changed, 41 insertions(+), 1 deletion(-) >> create mode 100644 board/altera/arria10-socdk/fit_spl_fpga_periph_only.its >> >> diff --git a/board/altera/arria10-socdk/fit_spl_fpga_periph_only.its >> b/board/altera/arria10-socdk/fit_spl_fpga_periph_only.its >> new file mode 100644 >> index 00000000000..06ba0328477 > > > Documentation: > https://github.com/u-boot/u-boot/blob/master/doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-mgr.txt > > still describe a single fit_spl_fpga.itb built from fit_spl_fpga.its. > > Please document the two-stage flow: which ITS produces which ITB,what > must be placed on the boot medium, > > and what SPL vs U-Boot proper load. > Two fixes: (1) wired altr,bitstream in the -u-boot.dtsi to the new periph-only .itb -- without this SPL still finds a core node in the old combined .itb and programs it, so v1 was a no-op in practice. (2) Added the two-stage flow to the fpga-mgr binding doc: which .its builds which .itb, and that both .itb files must stay on the boot medium (prog_core loads the combined one for fpga-core-1). > >> --- /dev/null >> +++ b/board/altera/arria10-socdk/fit_spl_fpga_periph_only.its >> @@ -0,0 +1,38 @@ >> +// SPDX-License-Identifier: GPL-2.0 >> + /* > > Comment block formatting after the SPDX line: avoid the stray space > before /* for consistency with common U-Boot style > will be updated! > >> + * Copyright (C) 2020 Intel Corporation <www.intel.com> > > Copyright year on the new file: align with current practice for new > contributions. > will be updated! > >> + * >> + */ >> + >> +/dts-v1/; >> + >> +/ { >> + description = "FIT image with FPGA bistream"; > > description = "FIT image with FPGA bistream"; — typo: bitstream (same > typo exists in fit_spl_fpga.its; fixing the new file at minimum would > help). > > >> + #address-cells = <1>; >> + >> + images { >> + fpga-periph-1 { >> + description = "FPGA peripheral bitstream"; >> + data = /incbin/("../../../ghrd_10as066n2.periph.rbf"); >> + type = "fpga"; >> + arch = "arm"; >> + compression = "none"; >> + }; >> + >> + fpga-core-1 { >> + description = "FPGA core bitstream"; >> + data = /incbin/("../../../ghrd_10as066n2.core.rbf"); >> + type = "fpga"; >> + arch = "arm"; >> + compression = "none"; >> + }; >> + }; >> + >> + configurations { >> + default = "config-1"; >> + config-1 { >> + description = "Boot with FPGA early IO release config"; >> + fpga = "fpga-periph-1"; >> + }; >> + }; >> +}; >> diff --git a/configs/socfpga_arria10_defconfig >> b/configs/socfpga_arria10_defconfig >> index b32f40ae408..1648e4bda4b 100644 >> --- a/configs/socfpga_arria10_defconfig >> +++ b/configs/socfpga_arria10_defconfig >> @@ -20,7 +20,7 @@ CONFIG_SPL_FIT=y >> CONFIG_DISTRO_DEFAULTS=y >> CONFIG_USE_BOOTARGS=y >> CONFIG_BOOTARGS="console=ttyS0,115200" >> -# CONFIG_USE_BOOTCOMMAND is not set >> +CONFIG_BOOTCOMMAND="run fatscript;run prog_core;bridge enable;run >> distro_bootcmd" > > > Changing from “no default bootcommand” to run fatscript; run prog_core; > bridge enable; run distro_bootcmd > is a strong default for all users of socfpga_arria10_defconfig. > > It assumes MMC, FAT, optional u-boot.scr, fit_spl_fpga.itb on the card, > and a > > sensible ordering with bridge enable after FPGA steps. > > Users booting from QSPI/NAND or without those files may get surprising > behavior. > > You can opt-in FPGA chain + clearer prog_core in > socfpga_arria10_socdk.h, see the example in next comment. > Dropped the override. v2 only adds CONFIG_CMD_FPGA_LOADMK=y; default bootcmd is untouched. Two-stage flow is opt-in via "run bootcmd_fpga_mmc". One deviation from your snippet: dropped "run fatscript;" -- it doesn't exist in upstream mainline. Say the word if you want it added as its own thing. > >> CONFIG_DEFAULT_FDT_FILE="socfpga_arria10_socdk_sdmmc.dtb" >> CONFIG_SYS_CONSOLE_IS_IN_ENV=y >> CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y >> diff --git a/include/configs/socfpga_common.h >> b/include/configs/socfpga_common.h >> index 2acfdc7df4a..2c01bf9d9fa 100644 >> --- a/include/configs/socfpga_common.h >> +++ b/include/configs/socfpga_common.h >> @@ -154,6 +154,8 @@ >> "pxefile_addr_r=0x02200000\0" \ >> "ramdisk_addr_r=0x02300000\0" \ >> "socfpga_legacy_reset_compat=1\0" \ >> + "prog_core=if load mmc 0:1 ${loadaddr} fit_spl_fpga.itb;" \ >> + "then fpga loadmk 0 ${loadaddr}:fpga-core-1; fi\0" \ > > prog_core must not live in socfpga_common.h for all SoCFPGA boards. > Please move this to socfpga_arria10_socdk.h > > You can replace above with macro SOCFPGA_BOARD_ENV_APPEND. And define > the macro in socfpga_arria10_socdk.h > Done as specified: empty-by-default hook in socfpga_common.h, real definition (same QSPI/NAND guard) in socfpga_arria10_socdk.h. socfpga_common.h otherwise untouched. > /* > * SD/MMC boot uses CFG_EXTRA_ENV_SETTINGS from socfpga_common.h; append > * Arria 10 SOCdk-only variables here so other SoCFPGA boards are > unaffected. > * > * Default CONFIG_BOOTCOMMAND stays "run distro_bootcmd" (no MMC/FAT/FIT > * assumptions at autoboot). For two-stage FPGA (script, core > bitstream, bridges, > * then distro), run: bootcmd_fpga_mmc > * e.g. setenv bootcmd "run bootcmd_fpga_mmc"; saveenv > * or invoke that from u-boot.scr. > */ > #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_NAND_BOOT) > #define SOCFPGA_BOARD_ENV_APPEND \ > "prog_core=if load mmc 0:1 ${loadaddr} fit_spl_fpga.itb; then " \ > "if fpga loadmk 0 ${loadaddr}:fpga-core-1; then " \ > "echo prog_core: ok; " \ > "else echo prog_core: fpga_loadmk_failed; fi; " \ > "else echo prog_core: fit_load_failed; fi\0" \ > "bootcmd_fpga_mmc=run fatscript; run prog_core; bridge enable; " \ > "run distro_bootcmd\0" > #endif > > > Best regards, > > Tien Fong > please expect v2. Regards, Dinesh
