From: Alif Zakuan Yuslaimi <[email protected]> Add dedicated device tree support for the Terasic DE-25 Standard board, which is based on Agilex5.
Following Terasic's Linux device tree for DE-25 Standard configuration in which UART and board wiring differs from Altera SoCDK boards - enable UART1 instead of UART0, route console through serial0 alias, and expose a single HPS LED on GPIO port B pin 17 (active-low). Enable only the on-board peripherals present on this kit: a single RGMII Ethernet interface on gmac0 with PHY MDIO address 1, gpio1, i2c1, spi0, and usb0. The second GMAC, extra I2C/I3C buses, spi1, usb31, and NAND are left disabled. MMC retains UHS-I SDR104 mode consistent with the Altera SoCDK reference. QSPI NOR flash uses the SoCDK-style partition layout on the 256 MB device (dedicated u-boot and root regions); the QSPI controller is disabled in the U-Boot SPL device tree so that SD/MMC is the primary boot source. DRAM size is fixed at 1 GiB in the U-Boot additions. New files added: - socfpga_agilex5_de25s.dts: Main device tree - socfpga_agilex5_de25s-u-boot.dtsi: U-Boot specific additions - configs/socfpga_agilex5_de25s_defconfig: Board configuration Build system integration: - Add build target in Makefile for DE25 Standard device tree binary file Signed-off-by: Will <[email protected]> Signed-off-by: Alif Zakuan Yuslaimi <[email protected]> --- arch/arm/dts/Makefile | 1 + .../arm/dts/socfpga_agilex5_de25s-u-boot.dtsi | 203 ++++++++++++++++++ arch/arm/dts/socfpga_agilex5_de25s.dts | 157 ++++++++++++++ configs/socfpga_agilex5_de25s_defconfig | 3 + 4 files changed, 364 insertions(+) create mode 100644 arch/arm/dts/socfpga_agilex5_de25s-u-boot.dtsi create mode 100644 arch/arm/dts/socfpga_agilex5_de25s.dts create mode 100644 configs/socfpga_agilex5_de25s_defconfig diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index dada5f9eba2..3772af89c91 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -415,6 +415,7 @@ dtb-$(CONFIG_AM43XX) += am437x-gp-evm.dtb am437x-sk-evm.dtb \ dtb-$(CONFIG_TARGET_THUNDERX_88XX) += thunderx-88xx.dtb dtb-$(CONFIG_ARCH_SOCFPGA) += \ + socfpga_agilex5_de25s.dtb \ socfpga_agilex5_socdk.dtb \ socfpga_agilex5_socdk_emmc.dtb \ socfpga_arria5_secu1.dtb \ diff --git a/arch/arm/dts/socfpga_agilex5_de25s-u-boot.dtsi b/arch/arm/dts/socfpga_agilex5_de25s-u-boot.dtsi new file mode 100644 index 00000000000..4a5d9a4dca8 --- /dev/null +++ b/arch/arm/dts/socfpga_agilex5_de25s-u-boot.dtsi @@ -0,0 +1,203 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * U-Boot additions + * + * Copyright (C) 2026 Altera Corporation <www.altera.com> + */ + +#include "socfpga_agilex5-u-boot.dtsi" + +/{ + aliases { + spi0 = &qspi; + freeze_br0 = &freeze_controller; + }; + + soc { + freeze_controller: freeze_controller@0x20000450 { + compatible = "altr,freeze-bridge-controller"; + reg = <0x20000450 0x00000010>; + status = "disabled"; + }; + }; + + /* + * Both Memory base address and size default info is retrieved from HW setting. + * Reconfiguration / Overwrite these info can be done with examples below. + * + * When LPDDR ECC is enabled, the last 1/8 of the memory region must + * be reserved for the Inline ECC buffer. + * + * Example for memory size with 2GB: + * memory { + * reg = <0x0 0x80000000 0x0 0x80000000>; + * }; + * + * Example for memory size with 8GB: + * memory { + * reg = <0x0 0x80000000 0x0 0x80000000>, + * <0x8 0x80000000 0x1 0x80000000>; + * }; + * + * Example for memory size with 32GB: + * memory { + * reg = <0x0 0x80000000 0x0 0x80000000>, + * <0x8 0x80000000 0x7 0x80000000>; + * }; + * + * Example for memory size with 512GB: + * memory { + * reg = <0x0 0x80000000 0x0 0x80000000>, + * <0x8 0x80000000 0x7 0x80000000>, + * <0x88 0x00000000 0x78 0x00000000>; + * }; + * + * Example for memory size with 2GB with LPDDR Inline ECC ON: + * memory { + * reg = <0x0 0x80000000 0x0 0x70000000>; + * }; + * + * Example for memory size with 8GB with LPDDR Inline ECC ON: + * memory { + * reg = <0x0 0x80000000 0x0 0x80000000>, + * <0x8 0x80000000 0x1 0x40000000>; + * }; + */ + + memory { + reg = <0x0 0x80000000 0x0 0x40000000>; + }; + + chosen { + stdout-path = "serial0:115200n8"; + u-boot,spl-boot-order = &mmc,&flash0,&nand,"/memory"; + }; +}; + +&flash0 { + compatible = "jedec,spi-nor"; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + bootph-all; + /delete-property/ cdns,read-delay; +}; + +&flash1 { + bootph-all; +}; + +&i3c0 { + bootph-all; +}; + +&i3c1 { + bootph-all; +}; + +&gpio1 { + portb: gpio-controller@0 { + bootph-all; + }; +}; + +&sd_emmc_power { + bootph-all; +}; + +&sd_io_1v8_reg { + gpios = <&portb 3 GPIO_ACTIVE_HIGH>; + bootph-all; +}; + +&mmc { + status = "okay"; + + no-mmc; + disable-wp; + cap-sd-highspeed; + vmmc-supply = <&sd_emmc_power>; + vqmmc-supply = <&sd_io_1v8_reg>; + max-frequency = <200000000>; + sdhci-caps = <0x00000000 0x0000c800>; + + /* SD card default speed (DS) and UHS-I SDR12 mode timing configuration */ + cdns,phy-dqs-timing-delay-sd-ds = <0x00780000>; + cdns,phy-gate-lpbk-ctrl-delay-sd-ds = <0x81a40040>; + cdns,phy-dll-slave-ctrl-sd-ds = <0x00a000fe>; + cdns,phy-dq-timing-delay-sd-ds = <0x28000001>; + + /* SD card high speed and UHS-I SDR25 mode timing configuration */ + cdns,phy-dqs-timing-delay-sd-hs = <0x780001>; + cdns,phy-gate-lpbk-ctrl-delay-sd-hs = <0x81a40040>; + cdns,phy-dq-timing-delay-sd-hs = <0x10000001>; + cdns,ctrl-hrs16-slave-ctrl-sd-hs = <0x101>; + cdns,ctrl-hrs07-timing-delay-sd-hs = <0xA0001>; + + /* SD card UHS-I SDR50 mode timing configuration */ + cdns,phy-dqs-timing-delay-emmc-sdr = <0x780004>; + cdns,phy-gate-lpbk-ctrl-delay-emmc-sdr = <0x80a40040>; + cdns,phy-dll-slave-ctrl-emmc-sdr = <0x4000004>; + cdns,phy-dq-timing-delay-emmc-sdr = <0x38000001>; + cdns,ctrl-hrs09-timing-delay-emmc-sdr = <0xf1c1800c>; + cdns,ctrl-hrs10-lpbk-ctrl-delay-emmc-sdr = <0x20000>; + cdns,ctrl-hrs16-slave-ctrl-emmc-sdr = <0x101>; + cdns,ctrl-hrs07-timing-delay-emmc-sdr = <0x90005>; + + /* SD card UHS-I SDR104 mode timing configuration */ + cdns,phy-dq-timing-delay-emmc-hs200 = <0x11000001>; + cdns,phy-dqs-timing-delay-emmc-hs200 = <0x780004>; + cdns,phy-dll-slave-ctrl-emmc-hs200 = <0x4d4d00>; + cdns,phy-gate-lpbk-ctrl-delay-emmc-hs200 = <0x81a40040>; + cdns,ctrl-hrs09-timing-delay-emmc-hs200 = <0xf1c18000>; + cdns,ctrl-hrs10-lpbk-ctrl-delay-emmc-hs200 = <0x90000>; + cdns,ctrl-hrs16-slave-ctrl-emmc-hs200 = <0x101>; + cdns,ctrl-hrs07-timing-delay-emmc-hs200 = <0xa0001>; + + bootph-all; +}; + +&qspi { + status = "disabled"; +}; + +&nand { + bootph-all; +}; + +&timer0 { + bootph-all; +}; + +&timer1 { + bootph-all; +}; + +&timer2 { + bootph-all; +}; + +&timer3 { + bootph-all; +}; + +&watchdog0 { + bootph-all; +}; + +&gmac0 { + status = "okay"; + /* PHY delays is configured via skew properties */ + phy-mode = "rgmii"; + phy-handle = <&emac0_phy0>; + + max-frame-size = <9000>; + + mdio0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwxgmac-mdio"; + emac0_phy0: ethernet-phy@1 { + reg = <1>; + }; + }; +}; diff --git a/arch/arm/dts/socfpga_agilex5_de25s.dts b/arch/arm/dts/socfpga_agilex5_de25s.dts new file mode 100644 index 00000000000..6f7666e7a8b --- /dev/null +++ b/arch/arm/dts/socfpga_agilex5_de25s.dts @@ -0,0 +1,157 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2026 Altera Corporation <www.altera.com> + */ +#include "socfpga_agilex5.dtsi" + +/ { + model = "SoCFPGA Agilex5 Terasic DE25-Standard"; + + aliases { + serial0 = &uart1; + ethernet0 = &gmac0; + }; + + leds { + compatible = "gpio-leds"; + hps0 { + label = "hps_led0"; + gpios = <&portb 17 GPIO_ACTIVE_LOW>; + }; + }; + + memory { + device_type = "memory"; + /* We expect the bootloader to fill in the reg */ + reg = <0 0 0 0>; + }; + + soc { + clocks { + osc1 { + clock-frequency = <25000000>; + }; + }; + }; +}; + +&gpio1 { + status = "okay"; +}; + +&i2c1 { + status = "okay"; +}; + +&mmc { + sd-uhs-sdr104; + sdhci-caps-mask = <0x00002000 0x0000ff00>; +}; + +&uart1 { + status = "okay"; + bootph-all; +}; + +&usbphy0 { + status = "okay"; +}; + +&usb0 { + status = "okay"; + disable-over-current; +}; + +&watchdog0 { + status = "okay"; +}; + +&watchdog1 { + status = "okay"; +}; + +&watchdog2 { + status = "okay"; +}; + +&watchdog3 { + status = "okay"; +}; + +&watchdog4 { + status = "okay"; +}; + +&timer0 { + status = "okay"; +}; + +&timer1 { + status = "okay"; +}; + +&timer2 { + status = "okay"; +}; + +&timer3 { + status = "okay"; +}; + +&spi0 { + status = "okay"; +}; + +&nand { + status = "disabled"; + + flash1: flash@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "u-boot"; + reg = <0 0x200000>; + }; + partition@200000 { + label = "root"; + reg = <0x200000 0x3fe00000>; + }; + }; +}; + +&qspi { + flash0: flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "mt25qu02g"; + reg = <0>; + spi-max-frequency = <100000000>; + + m25p,fast-read; + cdns,page-size = <256>; + cdns,block-size = <16>; + cdns,read-delay = <1>; + cdns,tshsl-ns = <50>; + cdns,tsd2d-ns = <50>; + cdns,tchsh-ns = <4>; + cdns,tslch-ns = <4>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + qspi_boot: partition@0 { + label = "u-boot"; + reg = <0x0 0x04200000>; + }; + + root: partition@4200000 { + label = "root"; + reg = <0x04200000 0x0BE00000>; + }; + }; + }; +}; diff --git a/configs/socfpga_agilex5_de25s_defconfig b/configs/socfpga_agilex5_de25s_defconfig new file mode 100644 index 00000000000..6b99626f2ab --- /dev/null +++ b/configs/socfpga_agilex5_de25s_defconfig @@ -0,0 +1,3 @@ +#include <configs/socfpga_agilex5_defconfig> + +CONFIG_DEFAULT_DEVICE_TREE="socfpga_agilex5_de25s" -- 2.43.7
