On Thu, 2026-07-16 at 11:43 +0200, Yannic Moog wrote: > Hi INgo, > > On Thu, 2026-07-09 at 16:34 +0200, INgo Rah wrote: > > Updated RAM timings with new generated settings using > > DDR Tool v3.6.0_22-aa018543. > > Provide functions for 1GB, 4GB and revision 7 variants. > > > > Signed-off-by: INgo Rah <[email protected]> > > Reviewed-by: Gregor Herburger <[email protected]> > > Reviewed-by: Benedikt Spranger <[email protected]> > > --- > > board/phytec/phycore_imx8mm/lpddr4_timing.c | 1867 > > +++++++++++++-------------- > > board/phytec/phycore_imx8mm/lpddr4_timing.h | 13 + > > 2 files changed, 921 insertions(+), 959 deletions(-) > > > > diff --git a/board/phytec/phycore_imx8mm/lpddr4_timing.c > > b/board/phytec/phycore_imx8mm/lpddr4_timing.c > > index f5a2f3268b3..162b0209d92 100644 > > --- a/board/phytec/phycore_imx8mm/lpddr4_timing.c > > +++ b/board/phytec/phycore_imx8mm/lpddr4_timing.c > > @@ -1,16 +1,17 @@ > > // SPDX-License-Identifier: GPL-2.0-or-later > > /* > > - * Copyright 2019 NXP > > - * Copyright (C) 2023 PHYTEC Messtechnik GmbH > > + * Copyright 2025 NXP > > + * Copyright 2025 PHYTEC Messtechnik GmbH > > * > > - * Generated code from MX8M_DDR_tool > > + * Code partially generated with DDR Tool v3.6.0_22-aa018543. > > + * DDR PHY FW2017.09 > > */ > > > > #include <linux/kernel.h> > > #include <asm/arch/ddr.h> > > > > > > [...] > > > + > > +void set_dram_timings_1gb(void) > > +{ > > + dram_timing.ddrc_cfg[5].val = 0x2d0087; > > + dram_timing.ddrc_cfg[21].val = 0x8d; > > + dram_timing.ddrc_cfg[42].val = 0xf070707; > > +} > > + > > +void set_dram_timings_4gb(void) > > +{ > > + dram_timing.ddrc_cfg[2].val = 0xa3080020; > > + dram_timing.ddrc_cfg[37].val = 0x17; > > + dram_timing.fsp_msg[0].fsp_cfg[8].val = 0x310; > > + dram_timing.fsp_msg[0].fsp_cfg[20].val = 0x3; > > + dram_timing.fsp_msg[1].fsp_cfg[11].val = 0x310; > > + dram_timing.fsp_msg[1].fsp_cfg[23].val = 0x3; > > +} > > I think there is an error in the 4gb timings. At least when I use the timing > values you > referenced > in your cover letter (commit 00ac765d6032), 4GB RAM variant does boot > correctly. With these > timing > values, it does not.
I have to take back my statement. The timings do work, I had made errors during my testing efforts. After clean test setup, 4GiB does boot normally. So I can give you Tested-by: Yannic Moog <[email protected]> > > Also, for easier troubleshooting (i.e. bisect), I suggest to first add 1GB > and 4GB support and > after that create another commit that updates the timings. > > Yannic > > > + > > +void set_dram_timings_rev7(void) > > +{ > > + dram_timing.ddrc_cfg[10].val = 0x55004d; > > + dram_timing.ddrphy_cfg[64].val = 0x618; > > + dram_timing.ddrphy_cfg[65].val = 0x618; > > + dram_timing.ddrphy_cfg[66].val = 0x618; > > + dram_timing.ddrphy_cfg[67].val = 0x618; > > + dram_timing.ddrphy_cfg[68].val = 0x618; > > + dram_timing.ddrphy_cfg[69].val = 0x618; > > + dram_timing.ddrphy_cfg[70].val = 0x618; > > + dram_timing.ddrphy_cfg[71].val = 0x618; > > + dram_timing.ddrphy_cfg[72].val = 0x63; > > + dram_timing.ddrphy_cfg[73].val = 0x63; > > + dram_timing.ddrphy_cfg[74].val = 0x63; > > + dram_timing.ddrphy_cfg[75].val = 0x63; > > + dram_timing.ddrphy_cfg[76].val = 0x63; > > + dram_timing.ddrphy_cfg[77].val = 0x63; > > + dram_timing.ddrphy_cfg[78].val = 0x63; > > + dram_timing.ddrphy_cfg[79].val = 0x63; > > + dram_timing.ddrphy_cfg[80].val = 0x63; > > + dram_timing.ddrphy_cfg[81].val = 0x63; > > + dram_timing.fsp_msg[0].fsp_cfg[3].val = 0x3c30; > > + dram_timing.fsp_msg[0].fsp_cfg[11].val = 0x4d55; > > + dram_timing.fsp_msg[0].fsp_cfg[16].val = 0x4d55; > > + dram_timing.fsp_msg[0].fsp_cfg[23].val = 0x5500; > > + dram_timing.fsp_msg[0].fsp_cfg[29].val = 0x5500; > > + dram_timing.fsp_msg[1].fsp_cfg[3].val = 0x3c30; > > + dram_timing.fsp_msg[1].fsp_cfg[14].val = 0x4d55; > > + dram_timing.fsp_msg[1].fsp_cfg[19].val = 0x4d55; > > + dram_timing.fsp_msg[1].fsp_cfg[26].val = 0x5500; > > + dram_timing.fsp_msg[1].fsp_cfg[32].val = 0x5500; > > +} > > diff --git a/board/phytec/phycore_imx8mm/lpddr4_timing.h > > b/board/phytec/phycore_imx8mm/lpddr4_timing.h > > new file mode 100644 > > index 00000000000..340fefe01c3 > > --- /dev/null > > +++ b/board/phytec/phycore_imx8mm/lpddr4_timing.h > > @@ -0,0 +1,13 @@ > > +/* SPDX-License-Identifier: GPL-2.0-or-later */ > > +/* > > + * Copyright (C) 2025 PHYTEC Messtechnik GmbH > > + */ > > + > > +#ifndef __LPDDR4_TIMING_H__ > > +#define __LPDDR4_TIMING_H__ > > + > > +void set_dram_timings_1gb(void); > > +void set_dram_timings_4gb(void); > > +void set_dram_timings_rev7(void); > > + > > +#endif /* __LPDDR4_TIMING_H__ */
