Current rockchip,rk3528-saradc fallback instruct the driver to use a 1 GHz clock rate. However, the CLK_SARADC used on RK3506 can only be configured to use a 32 KHz, 400 KHz or 1.5-24 GHz rate.
Add driver data for rockchip,rk3506-saradc that request use of a 1.5 GHz clock rate, to avoid clock divider overflow in the RK3506 clock driver. Signed-off-by: Jonas Karlman <[email protected]> --- drivers/adc/rockchip-saradc.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/adc/rockchip-saradc.c b/drivers/adc/rockchip-saradc.c index 1515951403c9..50861b61eea4 100644 --- a/drivers/adc/rockchip-saradc.c +++ b/drivers/adc/rockchip-saradc.c @@ -339,6 +339,14 @@ static const struct rockchip_saradc_data rk3399_saradc_data = { .stop = rockchip_saradc_stop_v1, }; +static const struct rockchip_saradc_data rk3506_saradc_data = { + .num_bits = 10, + .num_channels = 4, + .clk_rate = 1500000, + .channel_data = rockchip_saradc_channel_data_v2, + .start_channel = rockchip_saradc_start_channel_v2, +}; + static const struct rockchip_saradc_data rk3528_saradc_data = { .num_bits = 10, .num_channels = 4, @@ -362,6 +370,8 @@ static const struct udevice_id rockchip_saradc_ids[] = { .data = (ulong)&rk3066_tsadc_data }, { .compatible = "rockchip,rk3399-saradc", .data = (ulong)&rk3399_saradc_data }, + { .compatible = "rockchip,rk3506-saradc", + .data = (ulong)&rk3506_saradc_data }, { .compatible = "rockchip,rk3528-saradc", .data = (ulong)&rk3528_saradc_data }, { .compatible = "rockchip,rk3588-saradc", -- 2.54.0
