From: Macpaul Lin <[email protected]> Add MT8366 application processor .dtsi file for systems based on this chip.
Upstreaming of MT8366 has not even started yet, so we will have to carry a downstream version of this for some time. Signed-off-by: Macpaul Lin <[email protected]> Signed-off-by: David Lechner <[email protected]> --- arch/arm/dts/mt8366.dtsi | 662 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 662 insertions(+) diff --git a/arch/arm/dts/mt8366.dtsi b/arch/arm/dts/mt8366.dtsi new file mode 100644 index 00000000000..263b0149a85 --- /dev/null +++ b/arch/arm/dts/mt8366.dtsi @@ -0,0 +1,662 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2025 MediaTek Inc. + * Author: Macpaul Lin <[email protected]> + */ + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/pinctrl/mediatek,mt8366-pinfunc.h> +#include <dt-bindings/phy/phy.h> +#include <dt-bindings/clock/mt8366-clk.h> + +/ { + compatible = "mediatek,mt8366"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + serial0 = &uart0; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + i2c5 = &i2c5; + i2c6 = &i2c6; + i2c7 = &i2c7; + i2c8 = &i2c8; + i2c9 = &i2c9; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + + core1 { + cpu = <&cpu1>; + }; + + core2 { + cpu = <&cpu2>; + }; + + core3 { + cpu = <&cpu3>; + }; + + core4 { + cpu = <&cpu4>; + }; + }; + + cluster1 { + core0 { + cpu = <&cpu5>; + }; + }; + }; + + cpu0: cpu@0 { + compatible = "arm,cortex-a55", "arm,armv8"; + reg = <0x000>; + enable-method = "psci"; + capacity-dmips-mhz = <282>; + }; + + cpu1: cpu@1 { + compatible = "arm,cortex-a55", "arm,armv8"; + reg = <0x100>; + enable-method = "psci"; + capacity-dmips-mhz = <282>; + }; + + cpu2: cpu@2 { + compatible = "arm,cortex-a55", "arm,armv8"; + reg = <0x200>; + enable-method = "psci"; + capacity-dmips-mhz = <282>; + }; + + cpu3: cpu@3 { + compatible = "arm,cortex-a55", "arm,armv8"; + reg = <0x300>; + enable-method = "psci"; + capacity-dmips-mhz = <282>; + }; + + cpu4: cpu@4 { + compatible = "arm,cortex-a55", "arm,armv8"; + reg = <0x400>; + enable-method = "psci"; + capacity-dmips-mhz = <282>; + }; + + cpu5: cpu@600 { + compatible = "arm,cortex-a76", "arm,armv8"; + reg = <0x600>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + }; + }; + + clk26m: oscillator { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <26000000>; + clock-output-names = "clk26m"; + }; + + stmmac_axi_setup: stmmac-axi-config { + snps,wr-osr-lmt = <0x7>; + snps,rd-osr-lmt = <0x7>; + snps,blen = <0 0 0 0 16 8 4>; + }; + + mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use = <4>; + snps,rx-sched-sp; + + queue0 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x0>; + }; + + queue1 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x0>; + }; + + queue2 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x0>; + }; + + queue3 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x0>; + }; + }; + + mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use = <4>; + snps,tx-sched-wrr; + + queue0 { + snps,weight = <0x10>; + snps,dcb-algorithm; + snps,priority = <0x0>; + }; + + queue1 { + snps,weight = <0x11>; + snps,dcb-algorithm; + snps,priority = <0x1>; + }; + + queue2 { + snps,weight = <0x12>; + snps,dcb-algorithm; + snps,priority = <0x2>; + }; + + queue3 { + snps,weight = <0x13>; + snps,dcb-algorithm; + snps,priority = <0x3>; + }; + }; + + soc { + #address-cells = <2>; + #size-cells = <2>; + compatible = "simple-bus"; + ranges; + + watchdog: watchdog@10007000 { + compatible = "mediatek,wdt"; + reg = <0 0x10007000 0 0x100>; + status = "disabled"; + }; + + gic: interrupt-controller@c000000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <4>; + interrupt-parent = <&gic>; + interrupt-controller; + reg = <0 0x0c000000 0 0x40000>, /* GICD */ + <0 0x0c100000 0 0x200000>, /* GICR */ + <0 0x0c400000 0 0x2000>, /* GICC */ + <0 0x0c410000 0 0x1000>, /* GICH */ + <0 0x0c420000 0 0x2000>; /* GICV */ + + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; + + ppi-partitions { + ppi_cluster0: interrupt-partition-0 { + affinity = <&cpu0 &cpu1 &cpu2 &cpu3 &cpu4>; + }; + + ppi_cluster1: interrupt-partition-1 { + affinity = <&cpu5>; + }; + }; + }; + + topckgen_clk: clock-controller@10000000 { + compatible = "mediatek,mt8366-topckgen"; + reg = <0 0x10000000 0 0x1000>; + #clock-cells = <1>; + }; + + infracfg_ao_clk: clock-controller@10001000 { + compatible = "mediatek,mt8366-infracfg-ao", "syscon"; + reg = <0 0x10001000 0 0x1000>; + #clock-cells = <1>; + }; + + apmixedsys_clk: clock-controller@1000c000 { + compatible = "mediatek,mt8366-apmixedsys"; + reg = <0 0x1000c000 0 0x1000>; + #clock-cells = <1>; + }; + + gce_clk: clock-controller@10228000 { + compatible = "mediatek,mt8366-gce"; + reg = <0 0x10228000 0 0x1000>; + #clock-cells = <1>; + }; + + uart0: serial@11002000 { + compatible = "mediatek,hsuart"; + reg = <0 0x11002000 0 0x1000>; + interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_LOW 0>; + clock-frequency = <26000000>; + clocks = <&clk26m>, <&clk26m>; + clock-names = "baud", "bus"; + status = "disabled"; + }; + + spi0: spi@11010800 { + compatible = "mediatek,ipm-spi"; + reg = <0 0x11010800 0 0x100>; + interrupts = <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&infracfg_ao_clk CLK_INFRACFG_AO_REG_SPI0>; + clock-names = "spi-clk"; + status = "disabled"; + }; + + spi1: spi@11011800 { + compatible = "mediatek,ipm-spi"; + reg = <0 0x11011800 0 0x100>; + interrupts = <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&infracfg_ao_clk CLK_INFRACFG_AO_REG_SPI1>; + clock-names = "spi-clk"; + status = "disabled"; + }; + + spi2: spi@11012800 { + compatible = "mediatek,ipm-spi"; + reg = <0 0x11012800 0 0x100>; + interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&infracfg_ao_clk CLK_INFRACFG_AO_REG_SPI2>; + clock-names = "spi-clk"; + status = "disabled"; + }; + + spi3: spi@11013800 { + compatible = "mediatek,ipm-spi"; + reg = <0 0x11013800 0 0x100>; + interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&infracfg_ao_clk CLK_INFRACFG_AO_REG_SPI3>; + clock-names = "spi-clk"; + status = "disabled"; + }; + + spi4: spi@11014800 { + compatible = "mediatek,ipm-spi"; + reg = <0 0x11014800 0 0x100>; + interrupts = <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&infracfg_ao_clk CLK_INFRACFG_AO_REG_SPI4>; + clock-names = "spi-clk"; + status = "disabled"; + }; + + spi5: spi@11015800 { + compatible = "mediatek,ipm-spi"; + reg = <0 0x11015800 0 0x100>; + interrupts = <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&infracfg_ao_clk CLK_INFRACFG_AO_REG_SPI5>; + clock-names = "spi-clk"; + status = "disabled"; + }; + + i2c0: i2c@11fc0000 { + compatible = "mediatek,mt8171-i2c"; + reg = <0 0x11fc0000 0 0x1000>, + <0 0x10217080 0 0x200>; + interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&iic_wrap_e_clk CLK_IMPE_I2C0>, + <&infracfg_ao_clk CLK_INFRACFG_AO_REGP_DMA_B>; + clock-names = "main", "dma"; + clock-div = <1>; + }; + + i2c1: i2c@11290000 { + compatible = "mediatek,mt8171-i2c"; + reg = <0 0x11290000 0 0x1000>, + <0 0x10217280 0 0x200>; + interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&iic_wrap_c_clk CLK_IMPC_I2C1>, + <&infracfg_ao_clk CLK_INFRACFG_AO_REGP_DMA_B>; + clock-names = "main", "dma"; + clock-div = <1>; + }; + + i2c2: i2c@11291000 { + compatible = "mediatek,mt8171-i2c"; + reg = <0 0x11291000 0 0x1000>, + <0 0x10217480 0 0x80>; + interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&iic_wrap_c_clk CLK_IMPC_I2C2>, + <&infracfg_ao_clk CLK_INFRACFG_AO_REGP_DMA_B>; + clock-names = "main", "dma"; + clock-div = <1>; + }; + + i2c3: i2c@11292000 { + compatible = "mediatek,mt8171-i2c"; + reg = <0 0x11292000 0 0x1000>, + <0 0x10217500 0 0x80>; + interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&iic_wrap_c_clk CLK_IMPC_I2C3>, + <&infracfg_ao_clk CLK_INFRACFG_AO_REGP_DMA_B>; + clock-names = "main", "dma"; + clock-div = <1>; + }; + + i2c4: i2c@11fc1000 { + compatible = "mediatek,mt8171-i2c"; + reg = <0 0x11fc1000 0 0x1000>, + <0 0x10217580 0 0x80>; + interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&iic_wrap_e_clk CLK_IMPE_I2C4>, + <&infracfg_ao_clk CLK_INFRACFG_AO_REGP_DMA_B>; + clock-names = "main", "dma"; + clock-div = <1>; + }; + + i2c5: i2c@11293000 { + compatible = "mediatek,mt8171-i2c"; + reg = <0 0x11293000 0 0x1000>, + <0 0x10217600 0 0x80>; + interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&iic_wrap_c_clk CLK_IMPC_I2C5>, + <&infracfg_ao_clk CLK_INFRACFG_AO_REGP_DMA_B>; + clock-names = "main", "dma"; + clock-div = <1>; + }; + + i2c6: i2c@11294000 { + compatible = "mediatek,mt8171-i2c"; + reg = <0 0x11294000 0 0x1000>, + <0 0x10217680 0 0x80>; + interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&iic_wrap_c_clk CLK_IMPC_I2C6>, + <&infracfg_ao_clk CLK_INFRACFG_AO_REGP_DMA_B>; + clock-names = "main", "dma"; + clock-div = <1>; + }; + + i2c7: i2c@11295000 { + compatible = "mediatek,mt8171-i2c"; + reg = <0 0x11295000 0 0x1000>, + <0 0x10217700 0 0x80>; + interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&iic_wrap_c_clk CLK_IMPC_I2C7>, + <&infracfg_ao_clk CLK_INFRACFG_AO_REGP_DMA_B>; + clock-names = "main", "dma"; + clock-div = <1>; + }; + + i2c8: i2c@11296000 { + compatible = "mediatek,mt8171-i2c"; + reg = <0 0x11296000 0 0x1000>, + <0 0x10217780 0 0x80>; + interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&iic_wrap_c_clk CLK_IMPC_I2C8>, + <&infracfg_ao_clk CLK_INFRACFG_AO_REGP_DMA_B>; + clock-names = "main", "dma"; + clock-div = <1>; + }; + + i2c9: i2c@11297000 { + compatible = "mediatek,mt8171-i2c"; + reg = <0 0x11297000 0 0x1000>, + <0 0x10217800 0 0x80>; + interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&iic_wrap_c_clk CLK_IMPC_I2C9>, + <&infracfg_ao_clk CLK_INFRACFG_AO_REGP_DMA_B>; + clock-names = "main", "dma"; + clock-div = <1>; + }; + + eth: ethernet@11019000 { + compatible = "mediatek,mt8171-gmac", "snps,dwmac-5.10a"; + reg = <0 0x11019000 0 0x4000>; + interrupts = <GIC_SPI 527 IRQ_TYPE_LEVEL_HIGH 0>; + interrupt-names = "macirq"; + clock-names = "mac_main", + "ptp_ref", + "rmii_internal"; + clocks = <&topckgen_clk CLK_TOP_SNPS_ETH_250M_SEL>, + <&topckgen_clk CLK_TOP_SNPS_ETH_62P4M_PTP_SEL>, + <&topckgen_clk CLK_TOP_SNPS_ETH_50M_RMII_SEL>; + assigned-clocks = <&topckgen_clk CLK_TOP_SNPS_ETH_250M_SEL>, + <&topckgen_clk CLK_TOP_SNPS_ETH_62P4M_PTP_SEL>, + <&topckgen_clk CLK_TOP_SNPS_ETH_50M_RMII_SEL>; + assigned-clock-parents = <&topckgen_clk CLK_TOP_ETHPLL_D2>, + <&topckgen_clk CLK_TOP_ETHPLL_D8>, + <&topckgen_clk CLK_TOP_ETHPLL_D10>; + mediatek,pericfg = <&infracfg_ao_clk>; + snps,axi-config = <&stmmac_axi_setup>; + snps,mtl-rx-config = <&mtl_rx_setup>; + snps,mtl-tx-config = <&mtl_tx_setup>; + snps,txpbl = <16>; + snps,rxpbl = <16>; + clk-csr = <2>; + status = "disabled"; + }; + + mmc0: mmc@11230000 { + compatible = "mediatek,mt8366-mmc", "mediatek,mt8183-mmc"; + reg = <0 0x11230000 0 0x1000>, + <0 0x11ed0000 0 0x1000>; + interrupts-extended = <&gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&topckgen_clk CLK_TOP_MSDC50_0_SEL>, + <&infracfg_ao_clk CLK_INFRACFG_AO_REGP_MSDC0_H>, + <&infracfg_ao_clk CLK_INFRACFG_AO_REGP_MSDC0>; + clock-names = "source", "hclk", "source_cg"; + status = "disabled"; + }; + + pio: pinctrl@10005000 { + compatible = "mediatek,mt8366-pinctrl"; + reg = <0 0x10005000 0 0x1000>, + <0 0x11c30000 0 0x1000>, + <0 0x11d40000 0 0x1000>, + <0 0x11e20000 0 0x1000>, + <0 0x11ea0000 0 0x1000>, + <0 0x11f10000 0 0x1000>, + <0 0x11f20000 0 0x1000>; + reg-names = "gpio", "iocfg_rm", "iocfg_bm", + "iocfg_lb", "iocfg_tr", "iocfg_lt", + "iocfg_tl"; + + gpio: gpio-controller { + gpio-controller; + #gpio-cells = <2>; + }; + }; + + usb: usb@11200000 { + compatible = "mediatek,mtu3"; + reg = <0 0x11200000 0 0x3e00>, + <0 0x11203e00 0 0x0100>; + reg-names = "mac", "ippc"; + phy-cells = <1>; + phys = <&u2port0 PHY_TYPE_USB2>; + mediatek,u3p-dis-msk = <0x1>; + clocks = <&infracfg_ao_clk CLK_INFRACFG_AO_REGP_SSUSB0_XCHI>, + <&infracfg_ao_clk CLK_INFRACFG_AO_REGP_SSUSB0_SYS>, + <&infracfg_ao_clk CLK_INFRACFG_AO_REGP_SSUSB0_H>, + <&infracfg_ao_clk CLK_INFRACFG_AO_REGP_SSUSB0_F>, + <&infracfg_ao_clk CLK_INFRACFG_AO_REGP_SSUSB0_REF>, + <&infracfg_ao_clk CLK_INFRACFG_AO_REGP_SSUSB0_FRMCNT>; + clock-names = "host_ck", + "sys_ck", + "mcu_ck", + "dma_ck", + "ref_ck", + "frmcnt_ck"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + ssusb: ssusb@11200000 { + compatible = "mediatek,ssusb"; + reg = <0 0x11200000 0 0x3e00>; + reg-names = "mac"; + interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH 0>; + status = "disabled"; + }; + + xhci0: xhci@11200000 { + compatible = "mediatek,mtk-xhci"; + reg = <0 0x11200000 0 0x1000>; + reg-names = "mac"; + interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&infracfg_ao_clk CLK_INFRACFG_AO_REGP_SSUSB0_XCHI>; + clock-names = "xhci_ck"; + status = "disabled"; + }; + }; + + xhci1: xhci@11210000 { + compatible = "mediatek,mtk-xhci"; + reg = <0 0x11210000 0 0x1000>, + <0 0x11213e00 0 0x0100>; + reg-names = "mac", "ippc"; + interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH 0>; + phy-cells = <1>; + phys = <&u2port1 PHY_TYPE_USB2>; + assigned-clocks = <&topckgen_clk CLK_TOP_USB_TOP_P1_SEL>, + <&topckgen_clk CLK_TOP_USB_XHCI_P1_SEL>; + assigned-clock-parents = <&topckgen_clk CLK_TOP_UNIVPLL_D5_D4>, + <&topckgen_clk CLK_TOP_UNIVPLL_D5_D4>; + clocks = <&infracfg_ao_clk CLK_INFRACFG_AO_REGP_SSUSB1_XCHI>, + <&infracfg_ao_clk CLK_INFRACFG_AO_REGP_SSUSB1_SYS>, + <&infracfg_ao_clk CLK_INFRACFG_AO_REGP_SSUSB1_H>, + <&infracfg_ao_clk CLK_INFRACFG_AO_REGP_SSUSB1_F>, + <&infracfg_ao_clk CLK_INFRACFG_AO_REGP_SSUSB1_REF>, + <&infracfg_ao_clk CLK_INFRACFG_AO_REGP_SSUSB1_FRMCNT>; + clock-names = "xhci_ck", + "sys_ck", + "mcu_ck", + "dma_ck", + "ref_ck", + "frmcnt_ck"; + maximum-speed = "high-speed"; + status = "disabled"; + }; + + xhci2: xhci@11220000 { + compatible = "mediatek,mtk-xhci"; + reg = <0 0x11220000 0 0x1000>, + <0 0x11223e00 0 0x0100>; + reg-names = "mac", "ippc"; + interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH 0>; + phy-cells = <1>; + phys = <&u2port2 PHY_TYPE_USB2>; + assigned-clocks = <&topckgen_clk CLK_TOP_USB_TOP_P2_SEL>, + <&topckgen_clk CLK_TOP_USB_XHCI_P2_SEL>; + assigned-clock-parents = <&topckgen_clk CLK_TOP_UNIVPLL_D5_D4>, + <&topckgen_clk CLK_TOP_UNIVPLL_D5_D4>; + clocks = <&infracfg_ao_clk CLK_INFRACFG_AO_REGP_SSUSB2_XCHI>, + <&infracfg_ao_clk CLK_INFRACFG_AO_REGP_SSUSB2_SYS>, + <&infracfg_ao_clk CLK_INFRACFG_AO_REGP_SSUSB2_H>, + <&infracfg_ao_clk CLK_INFRACFG_AO_REGP_SSUSB2_F>, + <&infracfg_ao_clk CLK_INFRACFG_AO_REGP_SSUSB2_REF>, + <&infracfg_ao_clk CLK_INFRACFG_AO_REGP_SSUSB2_FRMCNT>; + clock-names = "xhci_ck", + "sys_ck", + "mcu_ck", + "dma_ck", + "ref_ck", + "frmcnt_ck"; + status = "disabled"; + }; + + iic_wrap_c_clk: clock-controller@11298000 { + compatible = "mediatek,mt8366-iic-wrap-c"; + reg = <0 0x11298000 0 0x1000>; + #clock-cells = <1>; + }; + + snor: spi@11018000 { + compatible = "mediatek,mt8366-nor"; + reg = <0 0x11018000 0 0x1000>; + clocks = <&topckgen_clk CLK_TOP_SFLASH_SEL>, + <&infracfg_ao_clk CLK_INFRACFG_AO_REGP_SFLASH>, + <&infracfg_ao_clk CLK_INFRACFG_AO_REGP_SFLASH_F>, + <&infracfg_ao_clk CLK_INFRACFG_AO_REGP_SFLASH_H>, + <&infracfg_ao_clk CLK_INFRACFG_AO_REGP_SFLASH_P>; + clock-names = "spi", "sf", "axi_f", "axi_h", "axi_p"; + assigned-clocks = <&topckgen_clk CLK_TOP_SFLASH_SEL>; + assigned-clock-parents = <&topckgen_clk CLK_TOP_UNIVPLL_D6_D8>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + u2phy2: phy@11e40000 { + compatible = "mediatek,generic-tphy-v2"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + u2port2: usb2-phy2@11e40000 { + reg = <0 0x11e40000 0 0x700>; + clocks = <&topckgen_clk CLK_TOP_USB2_PHY_REFCK_P2_EN>; + clock-names = "ref"; + #phy-cells = <1>; + }; + }; + + u3phy0: phy@11e80000 { + compatible = "mediatek,generic-tphy-v2"; + reg = <0 0x11e80000 0 0x1000>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + u2port0: usb2-phy@11e80000 { + reg = <0 0x11e80000 0 0x700>; + #phy-cells = <1>; + clocks = <&topckgen_clk CLK_TOP_USB2_PHY_REFCK_P0_EN>; + clock-names = "ref"; + }; + }; + + dptx_clk: clock-controller@11ec1400 { + compatible = "mediatek,mt8366-dptx"; + reg = <0 0x11ec1400 0 0x1000>; + #clock-cells = <1>; + }; + + u2phy1: phy@11ef0000 { + compatible = "mediatek,generic-tphy-v2"; + reg = <0 0x11ef0000 0 0x1000>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + u2port1: usb2-phy1@11ef0000 { + reg = <0 0x11ef0000 0 0x700>; + clocks = <&topckgen_clk CLK_TOP_USB2_PHY_REFCK_P1_EN>; + clock-names = "ref"; + #phy-cells = <1>; + }; + }; + + iic_wrap_e_clk: clock-controller@11fc2000 { + compatible = "mediatek,mt8366-iic-wrap-e"; + reg = <0 0x11fc2000 0 0x1000>; + #clock-cells = <1>; + }; + + dispsys_clk: clock-controller@14000000 { + compatible = "mediatek,mt8366-dispsys"; + reg = <0 0x14000000 0 0x1000>; + #clock-cells = <1>; + }; + + epdsys_clk: clock-controller@1c000000 { + compatible = "mediatek,mt8366-epdsys"; + reg = <0 0x1c000000 0 0x1000>; + #clock-cells = <1>; + }; + }; +}; -- 2.43.0
