Hi Dinesh,
On Thu, 07 May 2026 08:55:38 +0800, [email protected] wrote:
The default load address of 0x01000000 falls within the 32MB region
reserved at the start of DDR. Bump it to 0x02000000 across all the
N5X SoCDK defconfigs to match the sibling Agilex / Stratix 10 SoCDK.
Nit (optional): the "32MB region reserved at the start of DDR" claim is
not cited in-tree. The stronger rationale is already in the patch —
ARCH_SOCFPGA defaults to 0x01000000, while Agilex/Stratix 10 SoCDK and
N5X SPL_LOAD_FIT_ADDRESS/scriptaddr already use the 0x02000000
convention. Fine to leave as-is or tighten in a follow-up.
"loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
"fdt_addr=1100000\0" \
"scriptaddr=0x02100000\0" \
Follow-up only (not a blocker for this patch): board env still
hard-codes fdt_addr=0x01100000 below the new loadaddr. Worth aligning
later if low DDR must stay clear of payloads.
Best regards,
Tien Fong
