Imported from Linux (v7.2-rc4) driver.
Reviewed-by: Casey Connolly <[email protected]>
Signed-off-by: Varadarajan Narayanan <[email protected]>
---
drivers/phy/qcom/phy-qcom-qusb2.c | 356 +++++++++++++++++++++++++++++++-------
1 file changed, 294 insertions(+), 62 deletions(-)
diff --git a/drivers/phy/qcom/phy-qcom-qusb2.c
b/drivers/phy/qcom/phy-qcom-qusb2.c
index 6278171b100..7a9cad7cacf 100644
--- a/drivers/phy/qcom/phy-qcom-qusb2.c
+++ b/drivers/phy/qcom/phy-qcom-qusb2.c
@@ -15,81 +15,81 @@
#include <dt-bindings/phy/phy-qcom-qusb2.h>
-#define QUSB2PHY_PLL 0x0
-#define QUSB2PHY_PLL_TEST 0x04
-#define CLK_REF_SEL BIT(7)
+#define QUSB2PHY_PLL 0x0
+#define QUSB2PHY_PLL_TEST 0x04
+#define CLK_REF_SEL BIT(7)
-#define QUSB2PHY_PLL_TUNE 0x08
-#define QUSB2PHY_PLL_USER_CTL1 0x0c
-#define QUSB2PHY_PLL_USER_CTL2 0x10
-#define QUSB2PHY_PLL_AUTOPGM_CTL1 0x1c
-#define QUSB2PHY_PLL_PWR_CTRL 0x18
+#define QUSB2PHY_PLL_TUNE 0x08
+#define QUSB2PHY_PLL_USER_CTL1 0x0c
+#define QUSB2PHY_PLL_USER_CTL2 0x10
+#define QUSB2PHY_PLL_AUTOPGM_CTL1 0x1c
+#define QUSB2PHY_PLL_PWR_CTRL 0x18
/* QUSB2PHY_PLL_STATUS register bits */
-#define PLL_LOCKED BIT(5)
+#define PLL_LOCKED BIT(5)
/* QUSB2PHY_PLL_COMMON_STATUS_ONE register bits */
-#define CORE_READY_STATUS BIT(0)
+#define CORE_READY_STATUS BIT(0)
/* QUSB2PHY_PORT_POWERDOWN register bits */
-#define CLAMP_N_EN BIT(5)
-#define FREEZIO_N BIT(1)
-#define POWER_DOWN BIT(0)
+#define CLAMP_N_EN BIT(5)
+#define FREEZIO_N BIT(1)
+#define POWER_DOWN BIT(0)
/* QUSB2PHY_PWR_CTRL1 register bits */
-#define PWR_CTRL1_VREF_SUPPLY_TRIM BIT(5)
-#define PWR_CTRL1_CLAMP_N_EN BIT(1)
+#define PWR_CTRL1_VREF_SUPPLY_TRIM BIT(5)
+#define PWR_CTRL1_CLAMP_N_EN BIT(1)
-#define QUSB2PHY_REFCLK_ENABLE BIT(0)
+#define QUSB2PHY_REFCLK_ENABLE BIT(0)
-#define PHY_CLK_SCHEME_SEL BIT(0)
+#define PHY_CLK_SCHEME_SEL BIT(0)
/* QUSB2PHY_INTR_CTRL register bits */
-#define DMSE_INTR_HIGH_SEL BIT(4)
-#define DPSE_INTR_HIGH_SEL BIT(3)
-#define CHG_DET_INTR_EN BIT(2)
-#define DMSE_INTR_EN BIT(1)
-#define DPSE_INTR_EN BIT(0)
+#define DMSE_INTR_HIGH_SEL BIT(4)
+#define DPSE_INTR_HIGH_SEL BIT(3)
+#define CHG_DET_INTR_EN BIT(2)
+#define DMSE_INTR_EN BIT(1)
+#define DPSE_INTR_EN BIT(0)
/* QUSB2PHY_PLL_CORE_INPUT_OVERRIDE register bits */
-#define CORE_PLL_EN_FROM_RESET BIT(4)
-#define CORE_RESET BIT(5)
-#define CORE_RESET_MUX BIT(6)
+#define CORE_PLL_EN_FROM_RESET BIT(4)
+#define CORE_RESET BIT(5)
+#define CORE_RESET_MUX BIT(6)
/* QUSB2PHY_IMP_CTRL1 register bits */
-#define IMP_RES_OFFSET_MASK GENMASK(5, 0)
-#define IMP_RES_OFFSET_SHIFT 0x0
+#define IMP_RES_OFFSET_MASK GENMASK(5, 0)
+#define IMP_RES_OFFSET_SHIFT 0x0
/* QUSB2PHY_PLL_BIAS_CONTROL_2 register bits */
-#define BIAS_CTRL2_RES_OFFSET_MASK GENMASK(5, 0)
-#define BIAS_CTRL2_RES_OFFSET_SHIFT 0x0
+#define BIAS_CTRL2_RES_OFFSET_MASK GENMASK(5, 0)
+#define BIAS_CTRL2_RES_OFFSET_SHIFT 0x0
/* QUSB2PHY_CHG_CONTROL_2 register bits */
-#define CHG_CTRL2_OFFSET_MASK GENMASK(5, 4)
-#define CHG_CTRL2_OFFSET_SHIFT 0x4
+#define CHG_CTRL2_OFFSET_MASK GENMASK(5, 4)
+#define CHG_CTRL2_OFFSET_SHIFT 0x4
/* QUSB2PHY_PORT_TUNE1 register bits */
-#define HSTX_TRIM_MASK GENMASK(7, 4)
-#define HSTX_TRIM_SHIFT 0x4
-#define PREEMPH_WIDTH_HALF_BIT BIT(2)
-#define PREEMPHASIS_EN_MASK GENMASK(1, 0)
-#define PREEMPHASIS_EN_SHIFT 0x0
+#define HSTX_TRIM_MASK GENMASK(7, 4)
+#define HSTX_TRIM_SHIFT 0x4
+#define PREEMPH_WIDTH_HALF_BIT BIT(2)
+#define PREEMPHASIS_EN_MASK GENMASK(1, 0)
+#define PREEMPHASIS_EN_SHIFT 0x0
/* QUSB2PHY_PORT_TUNE2 register bits */
-#define HSDISC_TRIM_MASK GENMASK(1, 0)
-#define HSDISC_TRIM_SHIFT 0x0
+#define HSDISC_TRIM_MASK GENMASK(1, 0)
+#define HSDISC_TRIM_SHIFT 0x0
-#define QUSB2PHY_PLL_ANALOG_CONTROLS_TWO 0x04
-#define QUSB2PHY_PLL_CLOCK_INVERTERS 0x18c
-#define QUSB2PHY_PLL_CMODE 0x2c
-#define QUSB2PHY_PLL_LOCK_DELAY 0x184
-#define QUSB2PHY_PLL_DIGITAL_TIMERS_TWO 0xb4
-#define QUSB2PHY_PLL_BIAS_CONTROL_1 0x194
-#define QUSB2PHY_PLL_BIAS_CONTROL_2 0x198
-#define QUSB2PHY_PWR_CTRL2 0x214
-#define QUSB2PHY_IMP_CTRL1 0x220
-#define QUSB2PHY_IMP_CTRL2 0x224
-#define QUSB2PHY_CHG_CTRL2 0x23c
+#define QUSB2PHY_PLL_ANALOG_CONTROLS_TWO 0x04
+#define QUSB2PHY_PLL_CLOCK_INVERTERS 0x18c
+#define QUSB2PHY_PLL_CMODE 0x2c
+#define QUSB2PHY_PLL_LOCK_DELAY 0x184
+#define QUSB2PHY_PLL_DIGITAL_TIMERS_TWO 0xb4
+#define QUSB2PHY_PLL_BIAS_CONTROL_1 0x194
+#define QUSB2PHY_PLL_BIAS_CONTROL_2 0x198
+#define QUSB2PHY_PWR_CTRL2 0x214
+#define QUSB2PHY_IMP_CTRL1 0x220
+#define QUSB2PHY_IMP_CTRL2 0x224
+#define QUSB2PHY_CHG_CTRL2 0x23c
struct qusb2_phy_init_tbl {
unsigned int offset;
@@ -152,6 +152,35 @@ enum qusb2phy_reg_layout {
.offset = o, .val = v, .in_layout = 1, \
}
+static const struct qusb2_phy_init_tbl ipq6018_init_tbl[] = {
+ QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL, 0x14),
+ QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE1, 0xF8),
+ QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE2, 0xB3),
+ QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE3, 0x83),
+ QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE4, 0xC0),
+ QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_TUNE, 0x30),
+ QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_USER_CTL1, 0x79),
+ QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_USER_CTL2, 0x21),
+ QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE5, 0x00),
+ QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_PWR_CTRL, 0x00),
+ QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TEST2, 0x14),
+ QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_TEST, 0x80),
+ QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_AUTOPGM_CTL1, 0x9F),
+};
+
+static const unsigned int ipq6018_regs_layout[] = {
+ [QUSB2PHY_PLL_STATUS] = 0x38,
+ [QUSB2PHY_PORT_TUNE1] = 0x80,
+ [QUSB2PHY_PORT_TUNE2] = 0x84,
+ [QUSB2PHY_PORT_TUNE3] = 0x88,
+ [QUSB2PHY_PORT_TUNE4] = 0x8c,
+ [QUSB2PHY_PORT_TUNE5] = 0x90,
+ [QUSB2PHY_PORT_TEST1] = 0x98,
+ [QUSB2PHY_PORT_TEST2] = 0x9c,
+ [QUSB2PHY_PORT_POWERDOWN] = 0xb4,
+ [QUSB2PHY_INTR_CTRL] = 0xbc,
+};
+
static const struct qusb2_phy_init_tbl sm6115_init_tbl[] = {
QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE1, 0xf8),
QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE2, 0x53),
@@ -176,19 +205,6 @@ static const unsigned int sm6115_regs_layout[] = {
[QUSB2PHY_PORT_POWERDOWN] = 0xb4, [QUSB2PHY_INTR_CTRL] = 0xbc,
};
-static const unsigned int ipq6018_regs_layout[] = {
- [QUSB2PHY_PLL_STATUS] = 0x38,
- [QUSB2PHY_PORT_TUNE1] = 0x80,
- [QUSB2PHY_PORT_TUNE2] = 0x84,
- [QUSB2PHY_PORT_TUNE3] = 0x88,
- [QUSB2PHY_PORT_TUNE4] = 0x8C,
- [QUSB2PHY_PORT_TUNE5] = 0x90,
- [QUSB2PHY_PORT_TEST1] = 0x98,
- [QUSB2PHY_PORT_TEST2] = 0x9C,
- [QUSB2PHY_PORT_POWERDOWN] = 0xB4,
- [QUSB2PHY_INTR_CTRL] = 0xBC,
-};
-
static const struct qusb2_phy_init_tbl msm8996_init_tbl[] = {
QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE1, 0xf8),
QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE2, 0xb3),
@@ -250,6 +266,17 @@ static const unsigned int qusb2_v2_regs_layout[] = {
[QUSB2PHY_INTR_CTRL] = 0x230,
};
+static const struct qusb2_phy_cfg ipq6018_phy_cfg = {
+ .tbl = ipq6018_init_tbl,
+ .tbl_num = ARRAY_SIZE(ipq6018_init_tbl),
+ .regs = ipq6018_regs_layout,
+
+ .disable_ctrl = POWER_DOWN,
+ .mask_core_ready = PLL_LOCKED,
+ /* autoresume not used */
+ .autoresume_en = BIT(0),
+};
+
static const struct qusb2_phy_cfg msm8996_phy_cfg = {
.tbl = msm8996_init_tbl,
.tbl_num = ARRAY_SIZE(msm8996_init_tbl),
@@ -310,6 +337,34 @@ static const struct qusb2_phy_cfg qusb2_v2_phy_cfg = {
.update_tune1_with_efuse = true,
};
+/* struct override_param - structure holding qusb2 v2 phy overriding param
+ * set override true if the device tree property exists and read and assign
+ * to value
+ */
+struct override_param {
+ bool override;
+ u8 value;
+};
+
+/*struct override_params - structure holding qusb2 v2 phy overriding params
+ * @imp_res_offset: rescode offset to be updated in IMP_CTRL1 register
+ * @hstx_trim: HSTX_TRIM to be updated in TUNE1 register
+ * @preemphasis: Amplitude Pre-Emphasis to be updated in TUNE1 register
+ * @preemphasis_width: half/full-width Pre-Emphasis updated via TUNE1
+ * @bias_ctrl: bias ctrl to be updated in BIAS_CONTROL_2 register
+ * @charge_ctrl: charge ctrl to be updated in CHG_CTRL2 register
+ * @hsdisc_trim: disconnect threshold to be updated in TUNE2 register
+ */
+struct override_params {
+ struct override_param imp_res_offset;
+ struct override_param hstx_trim;
+ struct override_param preemphasis;
+ struct override_param preemphasis_width;
+ struct override_param bias_ctrl;
+ struct override_param charge_ctrl;
+ struct override_param hsdisc_trim;
+};
+
/**
* struct qusb2_phy - structure holding qusb2 phy attributes
*
@@ -317,6 +372,8 @@ static const struct qusb2_phy_cfg qusb2_v2_phy_cfg = {
* @base: iomapped memory space for qubs2 phy
*
* @cfg_ahb_clk: AHB2PHY interface clock
+ * @ref_clk: phy reference clock
+ * @iface_clk: phy interface clock
* @phy_rst: phy reset control
*
* @cfg: phy config data
@@ -327,12 +384,56 @@ struct qusb2_phy {
void __iomem *base;
struct clk cfg_ahb_clk;
+ struct clk ref_clk;
+ struct clk iface_clk;
struct reset_ctl phy_rst;
+ struct override_params overrides;
+
const struct qusb2_phy_cfg *cfg;
bool has_se_clk_scheme;
+ bool phy_initialized;
+ enum phy_mode mode;
};
+static inline void qusb2_write_mask(void __iomem *base, u32 offset,
+ u32 val, u32 mask)
+{
+ u32 reg;
+
+ reg = readl(base + offset);
+ reg &= ~mask;
+ reg |= val & mask;
+ writel(reg, base + offset);
+
+ /* Ensure above write is completed */
+ readl(base + offset);
+}
+
+static inline void qusb2_setbits(void __iomem *base, u32 offset, u32 val)
+{
+ u32 reg;
+
+ reg = readl(base + offset);
+ reg |= val;
+ writel(reg, base + offset);
+
+ /* Ensure above write is completed */
+ readl(base + offset);
+}
+
+static inline void qusb2_clrbits(void __iomem *base, u32 offset, u32 val)
+{
+ u32 reg;
+
+ reg = readl(base + offset);
+ reg &= ~val;
+ writel(reg, base + offset);
+
+ /* Ensure above write is completed */
+ readl(base + offset);
+}
+
static inline void qusb2_phy_configure(void __iomem *base,
const unsigned int *regs,
const struct qusb2_phy_init_tbl tbl[],
@@ -348,6 +449,68 @@ static inline void qusb2_phy_configure(void __iomem *base,
}
}
+/*
+ * Update board specific PHY tuning override values if specified from
+ * device tree.
+ */
+static void qusb2_phy_override_phy_params(struct qusb2_phy *qphy)
+{
+ const struct qusb2_phy_cfg *cfg = qphy->cfg;
+ struct override_params *or = &qphy->overrides;
+
+ if (or->imp_res_offset.override)
+ qusb2_write_mask(qphy->base, QUSB2PHY_IMP_CTRL1,
+ or->imp_res_offset.value << IMP_RES_OFFSET_SHIFT,
+ IMP_RES_OFFSET_MASK);
+
+ if (or->bias_ctrl.override)
+ qusb2_write_mask(qphy->base, QUSB2PHY_PLL_BIAS_CONTROL_2,
+ or->bias_ctrl.value << BIAS_CTRL2_RES_OFFSET_SHIFT,
+ BIAS_CTRL2_RES_OFFSET_MASK);
+
+ if (or->charge_ctrl.override)
+ qusb2_write_mask(qphy->base, QUSB2PHY_CHG_CTRL2,
+ or->charge_ctrl.value << CHG_CTRL2_OFFSET_SHIFT,
+ CHG_CTRL2_OFFSET_MASK);
+
+ if (or->hstx_trim.override)
+ qusb2_write_mask(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE1],
+ or->hstx_trim.value << HSTX_TRIM_SHIFT,
+ HSTX_TRIM_MASK);
+
+ if (or->preemphasis.override)
+ qusb2_write_mask(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE1],
+ or->preemphasis.value << PREEMPHASIS_EN_SHIFT,
+ PREEMPHASIS_EN_MASK);
+
+ if (or->preemphasis_width.override) {
+ if (or->preemphasis_width.value ==
+ QUSB2_V2_PREEMPHASIS_WIDTH_HALF_BIT)
+ qusb2_setbits(qphy->base,
+ cfg->regs[QUSB2PHY_PORT_TUNE1],
+ PREEMPH_WIDTH_HALF_BIT);
+ else
+ qusb2_clrbits(qphy->base,
+ cfg->regs[QUSB2PHY_PORT_TUNE1],
+ PREEMPH_WIDTH_HALF_BIT);
+ }
+
+ if (or->hsdisc_trim.override)
+ qusb2_write_mask(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE2],
+ or->hsdisc_trim.value << HSDISC_TRIM_SHIFT,
+ HSDISC_TRIM_MASK);
+}
+
+static int qusb2_phy_set_mode(struct phy *phy,
+ enum phy_mode mode, int submode)
+{
+ struct qusb2_phy *qphy = dev_get_priv(phy->dev);
+
+ qphy->mode = mode;
+
+ return 0;
+}
+
static int qusb2phy_do_reset(struct qusb2_phy *qphy)
{
int ret;
@@ -387,6 +550,9 @@ static int qusb2phy_power_on(struct phy *phy)
qusb2_phy_configure(qphy->base, cfg->regs, cfg->tbl, cfg->tbl_num);
+ /* Override board specific PHY tuning values */
+ qusb2_phy_override_phy_params(qphy);
+
/* Enable the PHY */
clrbits_le32(qphy->base + cfg->regs[QUSB2PHY_PORT_POWERDOWN],
POWER_DOWN);
@@ -401,6 +567,12 @@ static int qusb2phy_power_on(struct phy *phy)
*/
qphy->has_se_clk_scheme = cfg->se_clk_scheme_default;
+ if (!qphy->has_se_clk_scheme) {
+ ret = clk_enable(&qphy->ref_clk);
+ if (ret)
+ return ret;
+ }
+
if (cfg->has_pll_test) {
if (!qphy->has_se_clk_scheme)
val &= ~CLK_REF_SEL;
@@ -437,6 +609,8 @@ static int qusb2phy_power_off(struct phy *phy)
reset_assert(&qphy->phy_rst);
clk_disable(&qphy->cfg_ahb_clk);
+ clk_disable(&qphy->ref_clk);
+ clk_disable(&qphy->iface_clk);
return 0;
}
@@ -454,6 +628,22 @@ static int qusb2phy_clk_init(struct udevice *dev, struct
qusb2_phy *qphy)
if (ret)
return ret;
+ ret = clk_get_by_name(dev, "ref", &qphy->ref_clk);
+ if (ret == -ENOSYS || ret == -ENOENT)
+ return 0;
+ if (ret)
+ return ret;
+
+ ret = clk_get_by_name(dev, "iface", &qphy->iface_clk);
+ if (ret == -ENOSYS || ret == -ENOENT)
+ return 0;
+ if (ret)
+ return ret;
+
+ ret = clk_enable(&qphy->iface_clk);
+ if (ret)
+ return ret;
+
ret = clk_enable(&qphy->cfg_ahb_clk);
if (ret)
return ret;
@@ -464,6 +654,8 @@ static int qusb2phy_clk_init(struct udevice *dev, struct
qusb2_phy *qphy)
static int qusb2phy_probe(struct udevice *dev)
{
struct qusb2_phy *qphy = dev_get_priv(dev);
+ struct override_params *or;
+ u32 value;
int ret;
qphy->base = (void __iomem *)dev_read_addr(dev);
@@ -488,6 +680,43 @@ static int qusb2phy_probe(struct udevice *dev)
return -EINVAL;
}
+ or = &qphy->overrides;
+
+ if (!dev_read_u32(dev, "qcom,imp-res-offset-value", &value)) {
+ or->imp_res_offset.value = (u8)value;
+ or->imp_res_offset.override = true;
+ }
+
+ if (!dev_read_u32(dev, "qcom,bias-ctrl-value", &value)) {
+ or->bias_ctrl.value = (u8)value;
+ or->bias_ctrl.override = true;
+ }
+
+ if (!dev_read_u32(dev, "qcom,charge-ctrl-value", &value)) {
+ or->charge_ctrl.value = (u8)value;
+ or->charge_ctrl.override = true;
+ }
+
+ if (!dev_read_u32(dev, "qcom,hstx-trim-value", &value)) {
+ or->hstx_trim.value = (u8)value;
+ or->hstx_trim.override = true;
+ }
+
+ if (!dev_read_u32(dev, "qcom,preemphasis-level", &value)) {
+ or->preemphasis.value = (u8)value;
+ or->preemphasis.override = true;
+ }
+
+ if (!dev_read_u32(dev, "qcom,preemphasis-width", &value)) {
+ or->preemphasis_width.value = (u8)value;
+ or->preemphasis_width.override = true;
+ }
+
+ if (!dev_read_u32(dev, "qcom,hsdisc-trim-value", &value)) {
+ or->hsdisc_trim.value = (u8)value;
+ or->hsdisc_trim.override = true;
+ }
+
debug("%s success qusb phy cfg %p\n", __func__, qphy->cfg);
return 0;
}
@@ -495,6 +724,7 @@ static int qusb2phy_probe(struct udevice *dev)
static struct phy_ops qusb2phy_ops = {
.power_on = qusb2phy_power_on,
.power_off = qusb2phy_power_off,
+ .set_mode = qusb2_phy_set_mode,
};
static const struct udevice_id qusb2phy_ids[] = {
@@ -507,6 +737,8 @@ static const struct udevice_id qusb2phy_ids[] = {
.data = (ulong)&qcs615_phy_cfg },
{ .compatible = "qcom,sdm660-qusb2-phy",
.data = (ulong)&sdm660_phy_cfg },
+ { .compatible = "qcom,ipq9574-qusb2-phy",
+ .data = (ulong)&ipq6018_phy_cfg },
{ .compatible = "qcom,sm6115-qusb2-phy",
.data = (ulong)&sm6115_phy_cfg },
{ .compatible = "qcom,qusb2-v2-phy", .data = (ulong)&qusb2_v2_phy_cfg },
--
2.34.1
