On 8/14/26 12:45, Vandhiadevan Karunamoorthy wrote:
Add a DM_SPI driver for the SPI-protocol personality of the Qualcomm
GENI Serial Engine, found inside a QUPv3 wrapper on Qualcomm SoCs
such as SDM845, SM8250 and SA8775P. The Serial Engine is shared
across UART/I2C/SPI protocols and needs firmware for the desired
protocol loaded into it before use, via the existing
qcom_geni_load_firmware() helper.
The driver supports both the CPU-driven FIFO transfer path and the
Serial Engine's own DMA engine (SE-DMA), selected per SPI bus via the
optional "qcom,se-dma-allowed" device tree property.
Based on the Linux GENI SPI driver and shared GENI SE helper code,
notably:
- commit 561de45f72bd ("spi: spi-geni-qcom: Add SPI driver support
for GENI based QUP"), for the base FIFO-mode driver structure.
- commit e5f0dfa78ac7 ("spi: spi-geni-qcom: Add support for SE DMA
mode"), for the SE-DMA transfer path.
- commit fe8aa1ba0783 ("soc: qcom: geni-se: Update Tx and Rx fifo
depth based on QUP HW version"), for the fifo-depth helper.
Add the register offsets and the fifo-depth helper needed by the new
driver to the shared include/soc/qcom/geni-se.h, and wire up the new
driver's Kconfig entry and Makefile rule.
Signed-off-by: Vandhiadevan Karunamoorthy
<[email protected]>
---
.../spi/qcom,geni-spi.txt | 44 ++
drivers/spi/Kconfig | 9 +
drivers/spi/Makefile | 1 +
drivers/spi/qcom_geni_spi.c | 735 ++++++++++++++++++
include/soc/qcom/geni-se.h | 32 +
5 files changed, 821 insertions(+)
create mode 100644 doc/device-tree-bindings/spi/qcom,geni-spi.txt
create mode 100644 drivers/spi/qcom_geni_spi.c
diff --git a/doc/device-tree-bindings/spi/qcom,geni-spi.txt
b/doc/device-tree-bindings/spi/qcom,geni-spi.txt
new file mode 100644
index 00000000..020de31a
--- /dev/null
+++ b/doc/device-tree-bindings/spi/qcom,geni-spi.txt
Sorry but what is this ???
We stopped using text bindings for years, and for the last 2 years
we're importing the Linux DT & bindings in dts/upstream/Bindings/ so why would
you add this ???
Please get some review _before_ sending and wasting maintainer's and reviewer's
time.
I won't review further until you submit something reasonable and properly
reviewed internally.
Neil
@@ -0,0 +1,44 @@
+Qualcomm GENI SPI controller
+
+The GENI SPI controller is the SPI-protocol personality of a Qualcomm
+GENI/QUPv3 Serial Engine (SE). Each SE sits inside a QUPv3 wrapper
+(compatible "qcom,geni-se-qup") and needs Serial Engine firmware for the
+SPI protocol loaded into it before use; see the qcom,geni-se-qup binding
+for the firmware-loading mechanism.
+
+Required properties:
+- compatible : must be "qcom,geni-spi"
+- reg : base address and size of the SE registers
+
+Optional properties:
+- qcom,se-dma-allowed : if present, use the SE's own DMA engine (SE-DMA)
+ for transfers instead of the CPU-driven FIFO path.
+
+SPI slave nodes are added as children as per the generic SPI bindings
+in spi-bus.txt (e.g. reg = <cs>, spi-max-frequency, spi-tx/rx-bus-width).
+
+Example:
+
+ qupv3_0: geni-se-qup@ac0000 {
+ compatible = "qcom,geni-se-qup";
+ reg = <0x00ac0000 0x6000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ spi0: spi@a80000 {
+ compatible = "qcom,geni-spi";
+ reg = <0x00a80000 0x4000>;
+ clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
+ clock-names = "se";
+ qcom,se-dma-allowed;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <48000000>;
+ };
+ };
+ };
<snip>
