Add nord-ride-u-boot.dtsi to describe the UFS PHY clocks and ufs_mem_phy node required by U-Boot's UFS driver.
This allows the UFS controller to probe successfully on the nord-ride platform. Signed-off-by: Aswin Murugan <[email protected]> --- arch/arm/dts/nord-ride-u-boot.dtsi | 57 ++++++++++++++++++++++++++++++ 1 file changed, 57 insertions(+) create mode 100644 arch/arm/dts/nord-ride-u-boot.dtsi diff --git a/arch/arm/dts/nord-ride-u-boot.dtsi b/arch/arm/dts/nord-ride-u-boot.dtsi new file mode 100644 index 00000000000..259da42afad --- /dev/null +++ b/arch/arm/dts/nord-ride-u-boot.dtsi @@ -0,0 +1,57 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include <dt-bindings/clock/qcom,nord-negcc.h> + +/ { + negcc: clock-controller@8900000 { + compatible = "qcom,nord-negcc"; + reg = <0x0 0x08900000 0x0 0xf4200>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + + ufs_mem_phy: phy@1d40000 { + compatible = "qcom,nord-qmp-ufs-phy", + "qcom,sm8650-qmp-ufs-phy"; + reg = <0x0 0x01d40000 0x0 0x2000>; + + clocks = <&xo_board_clk>, + <&negcc NE_GCC_UFS_PHY_PHY_AUX_CLK>; + clock-names = "ref", + "ref_aux"; + + #clock-cells = <1>; + #phy-cells = <0>; + + status = "okay"; + }; +}; + +&ufs_mem_hc { + clocks = <&negcc NE_GCC_UFS_PHY_AXI_CLK>, + <&negcc NE_GCC_AGGRE_NOC_UFS_PHY_AXI_CLK>, + <&negcc NE_GCC_UFS_PHY_AHB_CLK>, + <&negcc NE_GCC_UFS_PHY_UNIPRO_CORE_CLK>, + <&xo_board_clk>, + <&negcc NE_GCC_UFS_PHY_TX_SYMBOL_0_CLK>, + <&negcc NE_GCC_UFS_PHY_RX_SYMBOL_0_CLK>, + <&negcc NE_GCC_UFS_PHY_RX_SYMBOL_1_CLK>; + clock-names = "core_clk", + "bus_aggr_clk", + "iface_clk", + "core_clk_unipro", + "ref_clk", + "tx_lane0_sync_clk", + "rx_lane0_sync_clk", + "rx_lane1_sync_clk"; + + resets = <&negcc NE_GCC_UFS_PHY_BCR>; + reset-names = "rst"; + + phys = <&ufs_mem_phy>; + phy-names = "ufsphy"; +}; -- 2.34.1
