Add ENETC 0 (1Gbps Ethernet port) support for MR-NAVQ95 board. Enable MDIO as well since all the ENETC instances share the MDIO bus.
Signed-off-by: Elena Popa <[email protected]> --- arch/arm/dts/imx95-navq.dts | 59 +++++++++++++++++++++++++++++++++++++ 1 file changed, 59 insertions(+) diff --git a/arch/arm/dts/imx95-navq.dts b/arch/arm/dts/imx95-navq.dts index 581d725406b..eb4ce9c1082 100644 --- a/arch/arm/dts/imx95-navq.dts +++ b/arch/arm/dts/imx95-navq.dts @@ -18,6 +18,7 @@ compatible = "fsl,imx95-navq", "fsl,imx95"; aliases { + ethernet0 = &enetc_port0; gpio0 = &gpio1; gpio1 = &gpio2; gpio2 = &gpio3; @@ -85,6 +86,14 @@ dma-channels = <30>; }; +&enetc_port0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enetc0>; + phy-handle = <ðphy0>; + phy-mode = "rgmii-id"; + status = "okay"; +}; + &lpi2c3 { clock-frequency = <400000>; pinctrl-names = "default"; @@ -115,7 +124,57 @@ status = "okay"; }; +&netc_blk_ctrl { + status = "okay"; +}; + +&netc_emdio { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_emdio>; + status = "okay"; + + ethphy0: ethernet-phy@1 { + reg = <1>; + eee-broken-1000t; + reset-gpios = <&i2c3_gpio_expander_21 1 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <80000>; + }; +}; + +&netc_timer { + status = "okay"; +}; + +&netcmix_blk_ctrl { + status = "okay"; +}; + &scmi_iomuxc { + pinctrl_emdio: emdiogrp { + fsl,pins = < + IMX95_PAD_ENET2_MDC__NETCMIX_TOP_NETC_MDC 0x50e + IMX95_PAD_ENET2_MDIO__NETCMIX_TOP_NETC_MDIO 0x90e + >; + }; + + pinctrl_enetc0: enetc0grp { + fsl,pins = < + IMX95_PAD_ENET1_TD3__NETCMIX_TOP_ETH0_RGMII_TD3 0x50e + IMX95_PAD_ENET1_TD2__NETCMIX_TOP_ETH0_RGMII_TD2 0x50e + IMX95_PAD_ENET1_TD1__NETCMIX_TOP_ETH0_RGMII_TD1 0x50e + IMX95_PAD_ENET1_TD0__NETCMIX_TOP_ETH0_RGMII_TD0 0x50e + IMX95_PAD_ENET1_TX_CTL__NETCMIX_TOP_ETH0_RGMII_TX_CTL 0x57e + IMX95_PAD_ENET1_TXC__NETCMIX_TOP_ETH0_RGMII_TX_CLK 0x58e + IMX95_PAD_ENET1_RX_CTL__NETCMIX_TOP_ETH0_RGMII_RX_CTL 0x57e + IMX95_PAD_ENET1_RXC__NETCMIX_TOP_ETH0_RGMII_RX_CLK 0x58e + IMX95_PAD_ENET1_RD0__NETCMIX_TOP_ETH0_RGMII_RD0 0x57e + IMX95_PAD_ENET1_RD1__NETCMIX_TOP_ETH0_RGMII_RD1 0x57e + IMX95_PAD_ENET1_RD2__NETCMIX_TOP_ETH0_RGMII_RD2 0x57e + IMX95_PAD_ENET1_RD3__NETCMIX_TOP_ETH0_RGMII_RD3 0x57e + >; + }; + pinctrl_lpi2c3: lpi2c3grp { fsl,pins = < IMX95_PAD_GPIO_IO28__LPI2C3_SDA 0x40000b9e -- 2.43.0
