Add a brief introduction to LoongArch architecture, some notes on the implementation, and the toolchain supporting status.
Signed-off-by: Yao Zi <[email protected]> --- New patch since v3 doc/arch/index.rst | 1 + doc/arch/loongarch.rst | 30 ++++++++++++++++++++++++++++++ 2 files changed, 31 insertions(+) create mode 100644 doc/arch/loongarch.rst diff --git a/doc/arch/index.rst b/doc/arch/index.rst index 60c93b3b6640..10903b806d2c 100644 --- a/doc/arch/index.rst +++ b/doc/arch/index.rst @@ -9,6 +9,7 @@ Architecture-specific doc arc arm64 arm64.ffa + loongarch m68k mips nios2 diff --git a/doc/arch/loongarch.rst b/doc/arch/loongarch.rst new file mode 100644 index 000000000000..d744db6a4999 --- /dev/null +++ b/doc/arch/loongarch.rst @@ -0,0 +1,30 @@ +.. SPDX-License-Identifier: GPL-2.0-or-later +.. Copyright (C) 2026 Yao Zi <[email protected]> + +LoongArch +========= + +LoongArch is a RISC ISA developed by Loongson Technology. It currently defines +three variants: a reduced 32-bit version (LA32R), a standard 32-bit version +(LA32S) for embedded devices, and a 64-bit version (LA64). + +Notes +----- + +1. Currently U-Boot only runs on LA64 variant with the highest privilege level + (PLV0). + +2. LA64 is distinguished with 32-bit LoongArch with CONFIG_ARCH_LA64. + +3. U-Boot expects hardware-maintained coherency between I-D cache. Cache + topology is probed through CPUCFG; L2 and L3 caches, if present, must be + unified or instruction-only. This is true for all commercial LA64 hardware. + Refer to arch/loongarch/lib/cache.c for further description. + +Toolchain +--------- + +LoongArch is supported in upstream binutils, gcc, and LLVM. GCC 12.1 started to +support LA64, and GCC 16 started to support LA32. +`kernel.org <https://mirrors.edge.kernel.org/pub/tools/crosstool/>`_ provides +pre-built toolchain for both 32-bit and 64-bit LoongArch. -- 2.55.0
