On Tue, Aug 25, 2026 at 04:24:16AM +0000, Yixun Lan wrote:
> Due to SPL image running in a memory space constraint SRAM environment,
> so reduce the whole clock tree a bit to make it fit for final runtime
> requirement, only a subset clock tree is registered, which includes UART,
> SDHCI, I2C (TWSI), and their PLL/MPMU/APMU/APBC ancestors; while the
> full clock tree is retained in non-SPL build.
>
> Where surviving SPL CCU definitions reference parent clocks outside
> that subset tree, it will use "clock-dummy" as name of clock parent to
> ensure the framework still successfully resolves the parent clock lookup.
>
> Signed-off-by: Yixun Lan <[email protected]>
> ---
[...]
> /* APMU clocks start */
> +#if IS_ENABLED(CONFIG_SPL_BUILD)
> +static const char * const axi_clk_parents[] = {
> + "pll1_d8_307p2", "pll1_d6_409p6",
> +};
> +CCU_MUX_DIV_FC_DEFINE(CLK_APMU_AXICLK, axi_clk, axi_clk,
> + axi_clk_parents, ARRAY_SIZE(axi_clk_parents),
> + APMU_ACLK_CLK_CTRL, APMU_ACLK_CLK_CTRL, 1, 2,
> + BIT(4), 0, 1, 0);
> +#else
> static const char * const axi_clk_parents[] = {
> "pll1_d8_307p2", "pll1_d6_409p6",
> };
The SPL clock subset does not seem to include all the clocks described
in the commit message. For example, the SDH0/1/2 clocks are excluded
from the SPL build.
Is this intentional?
--
Best regards,
Tim Ouyang
