Hi Chukun, On 9/2/2026 12:01 PM, Chukun Pan wrote: > The HINLINK H28K is a single board computer based on the > RK3528 SoC. Add support for the HINLINK H28K board. > > Features tested on HINLINK H28K: > - SD-card boot > - eMMC boot > - Ethernet > > Signed-off-by: Chukun Pan <[email protected]> > --- > arch/arm/dts/rk3528-hinlink-h28k-u-boot.dtsi | 11 ++++ > arch/arm/mach-rockchip/rk3528/MAINTAINERS | 6 ++ > configs/hinlink-h28k-rk3528_defconfig | 64 ++++++++++++++++++++ > doc/board/rockchip/rockchip.rst | 1 + > 4 files changed, 82 insertions(+) > create mode 100644 arch/arm/dts/rk3528-hinlink-h28k-u-boot.dtsi > create mode 100644 configs/hinlink-h28k-rk3528_defconfig
[snip] > diff --git a/configs/hinlink-h28k-rk3528_defconfig > b/configs/hinlink-h28k-rk3528_defconfig > new file mode 100644 > index 000000000000..bcd87bc02381 > --- /dev/null > +++ b/configs/hinlink-h28k-rk3528_defconfig > @@ -0,0 +1,64 @@ > +CONFIG_ARM=y > +CONFIG_SKIP_LOWLEVEL_INIT=y > +CONFIG_COUNTER_FREQUENCY=24000000 > +CONFIG_ARCH_ROCKCHIP=y > +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3528-hinlink-h28k" > +CONFIG_ROCKCHIP_RK3528=y > +CONFIG_SYS_LOAD_ADDR=0xc00800 > +CONFIG_DEBUG_UART_BASE=0xFF9F0000 > +CONFIG_DEBUG_UART_CLOCK=24000000 > +CONFIG_DEBUG_UART=y > +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3528-hinlink-h28k.dtb" > +# CONFIG_DISPLAY_CPUINFO is not set > +CONFIG_BOARD_RNG_SEED=y > +CONFIG_SPL_MAX_SIZE=0x40000 > +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set > +CONFIG_CMD_MEMINFO=y > +CONFIG_CMD_MEMINFO_MAP=y > +CONFIG_CMD_ADC=y > +CONFIG_CMD_GPIO=y > +CONFIG_CMD_GPT=y > +CONFIG_CMD_MISC=y > +CONFIG_CMD_MMC=y > +CONFIG_CMD_USB=y > +CONFIG_CMD_ROCKUSB=y > +CONFIG_CMD_USB_MASS_STORAGE=y USB OTG port is not enabled in DT, so CMD_ROCKUSB and CMD_USB_MASS_STORAGE may not be needed unless there is pending DT updates that will enable use of USB OTG port. > +# CONFIG_CMD_SETEXPR is not set > +CONFIG_CMD_RNG=y > +CONFIG_CMD_REGULATOR=y > +# CONFIG_SPL_DOS_PARTITION is not set > +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks > assigned-clock-rates assigned-clock-parents" clock-names is not included in this lists for new boards, please drop clock-names form the list of properties to be removed from SPL. > +CONFIG_BUTTON=y > +CONFIG_BUTTON_ADC=y > +# CONFIG_USB_FUNCTION_FASTBOOT is not set > +CONFIG_ROCKCHIP_GPIO=y > +CONFIG_LED=y > +CONFIG_LED_GPIO=y > +CONFIG_SUPPORT_EMMC_RPMB=y > +CONFIG_MMC_DW=y > +CONFIG_MMC_DW_ROCKCHIP=y > +CONFIG_MMC_SDHCI=y > +CONFIG_MMC_SDHCI_SDMA=y > +CONFIG_MMC_SDHCI_ROCKCHIP=y > +CONFIG_DM_MDIO=y > +CONFIG_DWC_ETH_QOS=y > +CONFIG_DWC_ETH_QOS_ROCKCHIP=y > +CONFIG_PHY_REALTEK=y > +CONFIG_PHY_ROCKCHIP_INNO_USB2=y > +CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y The combphy seems to be used for PCIe in the DT, maybe we should enable following Kconfig options: CONFIG_PCI=y CONFIG_PCIE_DW_ROCKCHIP=y CONFIG_CMD_PCI=y along with correct PCIe Ethernet driver. > +CONFIG_REGULATOR_PWM=y > +CONFIG_DM_REGULATOR_GPIO=y > +CONFIG_PWM_ROCKCHIP=y > +CONFIG_BAUDRATE=1500000 > +CONFIG_DEBUG_UART_SHIFT=2 > +CONFIG_SYS_NS16550_MEM32=y > +CONFIG_USB=y > +CONFIG_USB_XHCI_HCD=y The DWC3 node is not enabled in DT, is this something that will follow in a future DT update? > +CONFIG_USB_EHCI_HCD=y > +CONFIG_USB_EHCI_GENERIC=y > +CONFIG_USB_DWC3=y > +CONFIG_USB_DWC3_GENERIC=y The DWC3 node is not enabled in DT, so USB_XHCI_HCD, USB_DWC3 and USB_DWC3_GENERIC may not be needed unless there is pending DT updates that will enable use of the OTG port. > +CONFIG_USB_GADGET=y > +CONFIG_USB_GADGET_DOWNLOAD=y > +CONFIG_USB_FUNCTION_ROCKUSB=y Only the USB HOST port is enabled in DT, do we need these USB gadget related Kconfig options? Regards, Jonas > +CONFIG_ERRNO_STR=y [snip]
