Describe the System Power Manager with the MM_INFRA and DISP domains and the SSUSB domain, and add the infra-ao syscon that its bus protection steps poke. Label the display and mm-infra clock controllers so the domains can reference them.
Add the power-domains properties to xhci1, xhci2 and xhci3. These were left out previously since we did not have the power controller yet. The power controller node, its domains and the clock and label names follow the MT8189 device tree that is in flight for Linux, so this part should match once that lands. The display clock controller keeps the "mediatek,mt8189-dispsys" compatible for now; upstream splits that register range into a separate mmsys node, which is left for whenever display support is added. Signed-off-by: David Lechner <[email protected]> --- arch/arm/dts/mt8189.dtsi | 52 ++++++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 50 insertions(+), 2 deletions(-) diff --git a/arch/arm/dts/mt8189.dtsi b/arch/arm/dts/mt8189.dtsi index c965b00bb5c..f3a350c51b8 100644 --- a/arch/arm/dts/mt8189.dtsi +++ b/arch/arm/dts/mt8189.dtsi @@ -8,6 +8,7 @@ #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/phy/phy.h> +#include <dt-bindings/power/mediatek,mt8189-power.h> #include <dt-bindings/reset/ti-syscon.h> / { @@ -144,6 +145,45 @@ compatible = "simple-bus"; ranges; + scpsys: syscon@1c001000 { + compatible = "mediatek,mt8189-scpsys", "syscon", "simple-mfd"; + reg = <0 0x1c001000 0 0x1000>; + + /* System Power Manager */ + spm: power-controller { + compatible = "mediatek,mt8189-power-controller"; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + + power-domain@MT8189_POWER_DOMAIN_MM_INFRA { + reg = <MT8189_POWER_DOMAIN_MM_INFRA>; + clocks = <&topckgen_clk CLK_TOP_MMINFRA_SEL>, + <&mminfra_config_clk CLK_MMINFRA_SMI>; + clock-names = "mminfra", "ss-mminfra"; + mediatek,infracfg = <&infracfg_ao>; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + + power-domain@MT8189_POWER_DOMAIN_DISP { + reg = <MT8189_POWER_DOMAIN_DISP>; + clocks = <&topckgen_clk CLK_TOP_DISP0_SEL>, + <&dispsys_config_clk CLK_MM_SMI_LARB>; + clock-names = "disp", "ss-disp"; + mediatek,infracfg = <&infracfg_ao>; + #power-domain-cells = <0>; + }; + }; + + power-domain@MT8189_POWER_DOMAIN_SSUSB { + reg = <MT8189_POWER_DOMAIN_SSUSB>; + mediatek,infracfg = <&infracfg_ao>; + #power-domain-cells = <0>; + }; + }; + }; + watchdog: watchdog@1c00a000 { compatible = "mediatek,mt8391-wdt", "mediatek,wdt"; @@ -240,6 +280,7 @@ <&pericfg_ao_clk CLK_PERAO_SSUSB1_FRMCNT>; clock-names = "sys_ck", "ref_ck","mcu_ck", "dma_ck", "xhci_ck", "frmcnt_ck"; + power-domains = <&spm MT8189_POWER_DOMAIN_SSUSB>; #address-cells = <1>; #size-cells = <0>; wakeup-source; @@ -264,6 +305,7 @@ <&pericfg_ao_clk CLK_PERAO_SSUSB2_FRMCNT>; clock-names = "sys_ck", "ref_ck","mcu_ck", "dma_ck", "xhci_ck", "frmcnt_ck"; + power-domains = <&spm MT8189_POWER_DOMAIN_SSUSB>; #address-cells = <1>; #size-cells = <0>; wakeup-source; @@ -313,6 +355,7 @@ <&pericfg_ao_clk CLK_PERAO_SSUSB3_FRMCNT>; clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck", "frmcnt_ck"; + power-domains = <&spm MT8189_POWER_DOMAIN_SSUSB>; #address-cells = <1>; #size-cells = <0>; wakeup-source; @@ -344,13 +387,18 @@ status = "disabled"; }; + infracfg_ao: syscon@10001000 { + compatible = "mediatek,mt8189-infra-ao", "syscon"; + reg = <0 0x10001000 0 0x1000>; + }; + clock-controller@1000c000 { compatible = "mediatek,mt8189-apmixedsys", "syscon"; reg = <0 0x1000c000 0 0x1000>; #clock-cells = <1>; }; - clock-controller@14000000 { + dispsys_config_clk: clock-controller@14000000 { compatible = "mediatek,mt8189-dispsys", "syscon"; reg = <0 0x14000000 0 0x1000>; #clock-cells = <1>; @@ -368,7 +416,7 @@ #clock-cells = <1>; }; - clock-controller@1e800000 { + mminfra_config_clk: clock-controller@1e800000 { compatible = "mediatek,mt8189-mm-infra", "syscon"; reg = <0 0x1e800000 0 0x1000>; #clock-cells = <1>; -- 2.43.0
