From: Andre Heider <[email protected]> Enable the two PCIe controllers along with their associated PHYs. They are routed to the M.2 M-key connector and to the PCIe slot.
Signed-off-by: Andre Heider <[email protected]> Link: https://patch.msgid.link/[email protected] Signed-off-by: Yixun Lan <[email protected]> [ upstream commit: d9ab0a855ba13f1db3ae16539348714c74010a22 ] (cherry picked from commit b526ec8833b7e7a646cdb7ebc7b8f0af14dd154d) --- dts/upstream/src/riscv/spacemit/k1-musepi-pro.dts | 38 +++++++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/dts/upstream/src/riscv/spacemit/k1-musepi-pro.dts b/dts/upstream/src/riscv/spacemit/k1-musepi-pro.dts index b284bf416880..898b537ba0bc 100644 --- a/dts/upstream/src/riscv/spacemit/k1-musepi-pro.dts +++ b/dts/upstream/src/riscv/spacemit/k1-musepi-pro.dts @@ -36,6 +36,14 @@ }; }; + reg_pcie_vcc_3v3: regulator-pcie-vcc3v3 { + compatible = "regulator-fixed"; + regulator-name = "PCIE_VCC3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + reg_vcc_4v: regulator-vcc-4v { compatible = "regulator-fixed"; regulator-name = "VCC4V0"; @@ -272,6 +280,36 @@ }; }; +&pcie1_phy { + pinctrl-names = "default"; + pinctrl-0 = <&pcie1_3_cfg>; + status = "okay"; +}; + +&pcie1_port { + phys = <&pcie1_phy>; + vpcie3v3-supply = <®_pcie_vcc_3v3>; +}; + +&pcie1 { + status = "okay"; +}; + +&pcie2_phy { + pinctrl-names = "default"; + pinctrl-0 = <&pcie2_4_cfg>; + status = "okay"; +}; + +&pcie2_port { + phys = <&pcie2_phy>; + vpcie3v3-supply = <®_pcie_vcc_3v3>; +}; + +&pcie2 { + status = "okay"; +}; + &qspi { pinctrl-names = "default"; pinctrl-0 = <&qspi_cfg>; -- 2.51.0
