Am Dienstag, 4. August 2026, 02:26:38 Mitteleuropäische Sommerzeit schrieb Jonas Karlman: > This series flag clock drivers for probe after bind in SPL builds for > a few RK35xx SoCs that require core PLLs and clocks to be initialized at > an early phase. > > This should help e.g. ensure SPLL is initialized correctly on RK3588 and > CPU core rate is initialized on RK3576 when booting from RAM/USB. > > The series may possible depend on the series "rockchip: Miscellaneous > RK35xx clock fixes" [1] for a clean apply. > > [1] https://patchwork.ozlabs.org/cover/2278934/
Tested-by: Heiko Stuebner <[email protected]> This and the misc fixes series together make my DSI panel work again, which seemingly broke somewhere in between. Thanks Heiko
