Hi Tze,
On 26-08-2026 08:23, [email protected] wrote:
From: Tze Yee Ng <[email protected]>
The PHY control register (0x2080) holds phony_dqs_timing (bits [9:4]),
which shifts the read-capture strobe relative to the data slices.
Extend the per-mode PHY configuration arrays with a "cdns,phy-ctrl-*"
entry (default 0x41F0) and program register 0x2080 during PHY
adjustment. This lets each speed mode - and each board via device tree -
select an appropriate value.
Signed-off-by: Tze Yee Ng <[email protected]>
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The PHY_CTRL default needs to be corrected. All six tables also use the
same 0x41F0, so this is not actually per-mode.
Please fix the defaults.
Regards,
Tanmay
