Re: [PATCH v5 15/21] arm: mach-k3: j721e: Enable LPM resume flow for J7200/J721e SOC

[Kumar, Udit]

On 9/15/2026 7:29 PM, Richard GENOUD wrote:
>>> +        k3_ddrss_lpddr4_exit_low_power(dev, &regs);
>>> +
>>> +        do_resume();
>>
>> could you check, if caches can be enabled before do_resume() call
> I've tested that on j7200 and j784s4, and it fails at resume:
> U-Boot SPL 2026.10-rc2-00046-g31003eca655b-dirty (Sep 15 2026 - 15:52:55
> +0200)
> SYSFW ABI: 4.0 (firmware rev 0x000b '11.2.12--v11.02.12 (Fancy Rat)')
> Initialized 4 DRAM controllers
> Skipping authentication on GP device
> Starting ATF on ARM64 core...
> 

You need to flush caches before starting DM

> [   82.967460] Enabling non-boot CPUs ...
> ERROR:   Timeout waiting for thread RX_SECURE_TRANSPORT_CHANNEL_ID to fill
> ERROR:   Thread RX_SECURE_TRANSPORT_CHANNEL_ID verification failed (-60)
> ERROR:   Message receive failed (-60)
> ERROR:   Failed to get response (-60)
> ERROR:   Transfer send failed (-60)
> ERROR:   Request to start core failed: -60
> [   83.998938] psci: failed to boot CPU1 (-22)
> [   84.003168] CPU1: failed to boot: -22
> [   84.006989] Error taking CPU1 up: -22