Add power domain support for MT8365.
The domain tables and bus-protection sequences mirror the Linux
mt8365-pm-domains.h data available at commit ffeebf7587f5
("pmdomain: mediatek: Convert all SoCs to new style regmap retrieval")
Signed-off-by: Julien Stephan <[email protected]>
---
drivers/power/domain/Makefile | 1 +
drivers/power/domain/mt8365-power-domain.c | 233 +++++++++++++++++++++++++++++
2 files changed, 234 insertions(+)
diff --git a/drivers/power/domain/Makefile b/drivers/power/domain/Makefile
index 66c448033ee..3b816ed3bed 100644
--- a/drivers/power/domain/Makefile
+++ b/drivers/power/domain/Makefile
@@ -21,6 +21,7 @@ obj-$(CONFIG_TARGET_MT7623) += mt2701-power-domain.o
obj-$(CONFIG_TARGET_MT7622)$(CONFIG_TARGET_MT7629) += mt7622-power-domain.o
obj-$(CONFIG_TARGET_MT8188) += mt8188-power-domain.o
obj-$(CONFIG_TARGET_MT8189) += mt8189-power-domain.o
+obj-$(CONFIG_TARGET_MT8365) += mt8365-power-domain.o
obj-$(CONFIG_TARGET_MT8366) += mt8366-power-domain.o
endif
obj-$(CONFIG_QCOM_RPMH_POWER_DOMAIN) += qcom-rpmhpd.o
diff --git a/drivers/power/domain/mt8365-power-domain.c
b/drivers/power/domain/mt8365-power-domain.c
new file mode 100644
index 00000000000..a7d2cfff1d7
--- /dev/null
+++ b/drivers/power/domain/mt8365-power-domain.c
@@ -0,0 +1,233 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2026 MediaTek Inc.
+ * Copyright (C) 2026 BayLibre, SAS.
+ * Author: Julien Stephan <[email protected]>
+ */
+
+#include <dm.h>
+#include <dt-bindings/power/mediatek,mt8365-power.h>
+#include <linux/bitops.h>
+
+#include "mtk-power-domain.h"
+
+#define MT8365_SPM_PWR_STATUS 0x180
+#define MT8365_SPM_PWR_STATUS_2ND 0x184
+
+#define MT8365_INFRA_TOPAXI_PROTECTEN_SET 0x2a0
+#define MT8365_INFRA_TOPAXI_PROTECTEN_CLR 0x2a4
+#define MT8365_INFRA_TOPAXI_PROTECTEN_STA1 0x228
+#define MT8365_INFRA_TOPAXI_PROTECTEN_1_SET 0x2a8
+#define MT8365_INFRA_TOPAXI_PROTECTEN_1_CLR 0x2ac
+#define MT8365_INFRA_TOPAXI_PROTECTEN_1_STA1 0x258
+#define MT8365_INFRA_TOPAXI_SI0_CTL 0x200
+#define MT8365_INFRA_TOPAXI_SI2_CTL 0x234
+#define MT8365_INFRA_NAO_TOPAXI_SI0_STA 0x0
+#define MT8365_INFRA_NAO_TOPAXI_SI2_STA 0x28
+#define MT8365_SMI_COMMON_CLAMP_EN 0x3c0
+#define MT8365_SMI_COMMON_CLAMP_EN_SET 0x3c4
+#define MT8365_SMI_COMMON_CLAMP_EN_CLR 0x3c8
+
+#define MT8365_INFRA_TOPAXI_PROTECTEN_MM_M0 BIT(1)
+#define MT8365_INFRA_TOPAXI_PROTECTEN_MDMCU_M1 BIT(2)
+#define MT8365_INFRA_TOPAXI_PROTECTEN_MMAPB_S BIT(6)
+#define MT8365_INFRA_TOPAXI_PROTECTEN_AP2CONN_AHB BIT(13)
+#define MT8365_INFRA_TOPAXI_PROTECTEN_CONN2INFRA_AHB BIT(14)
+#define MT8365_INFRA_TOPAXI_PROTECTEN_MFG_M0 BIT(21)
+#define MT8365_INFRA_TOPAXI_PROTECTEN_INFRA2MFG BIT(22)
+#define MT8365_INFRA_TOPAXI_PROTECTEN_MM2INFRA_AXI_GALS_SLV_0 BIT(10)
+#define MT8365_INFRA_TOPAXI_PROTECTEN_MM2INFRA_AXI_GALS_SLV_1 BIT(11)
+
+#define MT8365_INFRA_TOPAXI_PROTECTEN_1_MM2INFRA_AXI_GALS_MST_0 BIT(16)
+#define MT8365_INFRA_TOPAXI_PROTECTEN_1_MM2INFRA_AXI_GALS_MST_1 BIT(17)
+#define MT8365_INFRA_TOPAXI_PROTECTEN_1_CONN2INFRA_AXI_GALS_MST BIT(18)
+#define MT8365_INFRA_TOPAXI_PROTECTEN_1_CAM2MM_AXI_GALS_MST BIT(19)
+#define MT8365_INFRA_TOPAXI_PROTECTEN_1_INFRA2CONN_AHB_GALS_SLV BIT(21)
+#define MT8365_INFRA_TOPAXI_PROTECTEN_1_APU2AP BIT(2)
+#define MT8365_INFRA_TOPAXI_PROTECTEN_1_APU_CBIP_GALS_MST BIT(20)
+#define MT8365_INFRA_TOPAXI_PROTECTEN_1_PWRDNREQ_INFRA_GALS_ADB BIT(24)
+#define MT8365_INFRA_TOPAXI_PROTECTEN_1_PWRDNREQ_MP1_L2C_AFIFO BIT(27)
+#define MT8365_INFRA_TOPAXI_PROTECTEN_1_AUDIO_BUS_AUDIO_M BIT(28)
+#define MT8365_INFRA_TOPAXI_PROTECTEN_1_AUDIO_BUS_DSP_M BIT(30)
+#define MT8365_INFRA_TOPAXI_PROTECTEN_1_AUDIO_BUS_DSP_S BIT(31)
+
+#define MT8365_INFRA_TOPAXI_SI0_WAY_EN_MMAPB_S BIT(6)
+#define MT8365_INFRA_TOPAXI_SI2_WAY_EN_PERI_M1 BIT(5)
+#define MT8365_INFRA_NAO_TOPAXI_SI0_CTRL_UPDATED BIT(24)
+#define MT8365_INFRA_NAO_TOPAXI_SI2_CTRL_UPDATED BIT(14)
+
+#define MT8365_BUS_PROT_INFRA_WR_TOPAXI(_mask) \
+ BUS_PROT_WR(INFRA, _mask, \
+ MT8365_INFRA_TOPAXI_PROTECTEN_SET, \
+ MT8365_INFRA_TOPAXI_PROTECTEN_CLR, \
+ MT8365_INFRA_TOPAXI_PROTECTEN_STA1)
+
+#define MT8365_BUS_PROT_INFRA_WR_TOPAXI_1(_mask) \
+ BUS_PROT_WR(INFRA, _mask, \
+ MT8365_INFRA_TOPAXI_PROTECTEN_1_SET, \
+ MT8365_INFRA_TOPAXI_PROTECTEN_1_CLR, \
+ MT8365_INFRA_TOPAXI_PROTECTEN_1_STA1)
+
+#define MT8365_BUS_PROT_SMI_WR_CLAMP_EN_PORT(_port) \
+ BUS_PROT_WR(SMI, BIT(_port), \
+ MT8365_SMI_COMMON_CLAMP_EN_SET, \
+ MT8365_SMI_COMMON_CLAMP_EN_CLR, \
+ MT8365_SMI_COMMON_CLAMP_EN)
+
+static const struct mtk_scp_domain_data mt8365_scp_domain[] = {
+ [MT8365_POWER_DOMAIN_MM] = {
+ .sta_mask = PWR_STATUS_DISP,
+ .ctl_offs = 0x30c,
+ .pwr_sta_offs = MT8365_SPM_PWR_STATUS,
+ .pwr_sta2nd_offs = MT8365_SPM_PWR_STATUS_2ND,
+ .sram_pdn_bits = GENMASK(8, 8),
+ .sram_pdn_ack_bits = GENMASK(12, 12),
+ .bp_cfg = {
+ MT8365_BUS_PROT_INFRA_WR_TOPAXI_1(
+
MT8365_INFRA_TOPAXI_PROTECTEN_1_MM2INFRA_AXI_GALS_MST_0 |
+
MT8365_INFRA_TOPAXI_PROTECTEN_1_MM2INFRA_AXI_GALS_MST_1),
+ MT8365_BUS_PROT_INFRA_WR_TOPAXI(
+ MT8365_INFRA_TOPAXI_PROTECTEN_MM_M0 |
+ MT8365_INFRA_TOPAXI_PROTECTEN_MDMCU_M1 |
+
MT8365_INFRA_TOPAXI_PROTECTEN_MM2INFRA_AXI_GALS_SLV_0 |
+
MT8365_INFRA_TOPAXI_PROTECTEN_MM2INFRA_AXI_GALS_SLV_1),
+ BUS_PROT_WAY_EN(MT8365_INFRA_TOPAXI_SI0_WAY_EN_MMAPB_S,
+ MT8365_INFRA_TOPAXI_SI0_CTL,
+
MT8365_INFRA_NAO_TOPAXI_SI0_CTRL_UPDATED,
+ MT8365_INFRA_NAO_TOPAXI_SI0_STA),
+ BUS_PROT_WAY_EN(MT8365_INFRA_TOPAXI_SI2_WAY_EN_PERI_M1,
+ MT8365_INFRA_TOPAXI_SI2_CTL,
+
MT8365_INFRA_NAO_TOPAXI_SI2_CTRL_UPDATED,
+ MT8365_INFRA_NAO_TOPAXI_SI2_STA),
+ MT8365_BUS_PROT_INFRA_WR_TOPAXI(
+ MT8365_INFRA_TOPAXI_PROTECTEN_MMAPB_S),
+ },
+ },
+ [MT8365_POWER_DOMAIN_CONN] = {
+ .sta_mask = PWR_STATUS_CONN,
+ .ctl_offs = 0x032c,
+ .pwr_sta_offs = MT8365_SPM_PWR_STATUS,
+ .pwr_sta2nd_offs = MT8365_SPM_PWR_STATUS_2ND,
+ .sram_pdn_bits = 0,
+ .sram_pdn_ack_bits = 0,
+ .bp_cfg = {
+ MT8365_BUS_PROT_INFRA_WR_TOPAXI(
+ MT8365_INFRA_TOPAXI_PROTECTEN_AP2CONN_AHB),
+ MT8365_BUS_PROT_INFRA_WR_TOPAXI_1(
+
MT8365_INFRA_TOPAXI_PROTECTEN_1_CONN2INFRA_AXI_GALS_MST),
+ MT8365_BUS_PROT_INFRA_WR_TOPAXI(
+ MT8365_INFRA_TOPAXI_PROTECTEN_CONN2INFRA_AHB),
+ MT8365_BUS_PROT_INFRA_WR_TOPAXI_1(
+
MT8365_INFRA_TOPAXI_PROTECTEN_1_INFRA2CONN_AHB_GALS_SLV),
+ },
+ },
+ [MT8365_POWER_DOMAIN_MFG] = {
+ .sta_mask = PWR_STATUS_MFG,
+ .ctl_offs = 0x0338,
+ .pwr_sta_offs = MT8365_SPM_PWR_STATUS,
+ .pwr_sta2nd_offs = MT8365_SPM_PWR_STATUS_2ND,
+ .sram_pdn_bits = GENMASK(9, 8),
+ .sram_pdn_ack_bits = GENMASK(13, 12),
+ .bp_cfg = {
+ MT8365_BUS_PROT_INFRA_WR_TOPAXI(BIT(25)),
+ MT8365_BUS_PROT_INFRA_WR_TOPAXI(
+ MT8365_INFRA_TOPAXI_PROTECTEN_MFG_M0 |
+ MT8365_INFRA_TOPAXI_PROTECTEN_INFRA2MFG),
+ },
+ },
+ [MT8365_POWER_DOMAIN_AUDIO] = {
+ .sta_mask = BIT(24),
+ .ctl_offs = 0x0314,
+ .pwr_sta_offs = MT8365_SPM_PWR_STATUS,
+ .pwr_sta2nd_offs = MT8365_SPM_PWR_STATUS_2ND,
+ .sram_pdn_bits = GENMASK(12, 8),
+ .sram_pdn_ack_bits = GENMASK(17, 13),
+ .bp_cfg = {
+ MT8365_BUS_PROT_INFRA_WR_TOPAXI_1(
+
MT8365_INFRA_TOPAXI_PROTECTEN_1_PWRDNREQ_MP1_L2C_AFIFO |
+
MT8365_INFRA_TOPAXI_PROTECTEN_1_AUDIO_BUS_AUDIO_M),
+ },
+ },
+ [MT8365_POWER_DOMAIN_CAM] = {
+ .sta_mask = BIT(25),
+ .ctl_offs = 0x0344,
+ .pwr_sta_offs = MT8365_SPM_PWR_STATUS,
+ .pwr_sta2nd_offs = MT8365_SPM_PWR_STATUS_2ND,
+ .sram_pdn_bits = GENMASK(9, 8),
+ .sram_pdn_ack_bits = GENMASK(13, 12),
+ .bp_cfg = {
+ MT8365_BUS_PROT_INFRA_WR_TOPAXI_1(
+
MT8365_INFRA_TOPAXI_PROTECTEN_1_CAM2MM_AXI_GALS_MST),
+ MT8365_BUS_PROT_SMI_WR_CLAMP_EN_PORT(2),
+ },
+ },
+ [MT8365_POWER_DOMAIN_DSP] = {
+ .sta_mask = BIT(17),
+ .ctl_offs = 0x037C,
+ .pwr_sta_offs = MT8365_SPM_PWR_STATUS,
+ .pwr_sta2nd_offs = MT8365_SPM_PWR_STATUS_2ND,
+ .sram_pdn_bits = GENMASK(11, 8),
+ .sram_pdn_ack_bits = GENMASK(15, 12),
+ .bp_cfg = {
+ MT8365_BUS_PROT_INFRA_WR_TOPAXI_1(
+
MT8365_INFRA_TOPAXI_PROTECTEN_1_PWRDNREQ_INFRA_GALS_ADB |
+ MT8365_INFRA_TOPAXI_PROTECTEN_1_AUDIO_BUS_DSP_M
|
+
MT8365_INFRA_TOPAXI_PROTECTEN_1_AUDIO_BUS_DSP_S),
+ },
+ },
+ [MT8365_POWER_DOMAIN_VDEC] = {
+ .sta_mask = BIT(31),
+ .ctl_offs = 0x0370,
+ .pwr_sta_offs = MT8365_SPM_PWR_STATUS,
+ .pwr_sta2nd_offs = MT8365_SPM_PWR_STATUS_2ND,
+ .sram_pdn_bits = GENMASK(8, 8),
+ .sram_pdn_ack_bits = GENMASK(12, 12),
+ .bp_cfg = {
+ MT8365_BUS_PROT_SMI_WR_CLAMP_EN_PORT(3),
+ },
+ },
+ [MT8365_POWER_DOMAIN_VENC] = {
+ .sta_mask = BIT(21),
+ .ctl_offs = 0x0304,
+ .pwr_sta_offs = MT8365_SPM_PWR_STATUS,
+ .pwr_sta2nd_offs = MT8365_SPM_PWR_STATUS_2ND,
+ .sram_pdn_bits = GENMASK(8, 8),
+ .sram_pdn_ack_bits = GENMASK(12, 12),
+ .bp_cfg = {
+ MT8365_BUS_PROT_SMI_WR_CLAMP_EN_PORT(1),
+ },
+ },
+ [MT8365_POWER_DOMAIN_APU] = {
+ .sta_mask = BIT(16),
+ .ctl_offs = 0x0378,
+ .pwr_sta_offs = MT8365_SPM_PWR_STATUS,
+ .pwr_sta2nd_offs = MT8365_SPM_PWR_STATUS_2ND,
+ .sram_pdn_bits = GENMASK(14, 8),
+ .sram_pdn_ack_bits = GENMASK(21, 15),
+ .bp_cfg = {
+ MT8365_BUS_PROT_INFRA_WR_TOPAXI_1(
+ MT8365_INFRA_TOPAXI_PROTECTEN_1_APU2AP |
+
MT8365_INFRA_TOPAXI_PROTECTEN_1_APU_CBIP_GALS_MST),
+ MT8365_BUS_PROT_SMI_WR_CLAMP_EN_PORT(4),
+ },
+ },
+};
+
+MTK_SCP_SOC_DATA(mt8365, mt8365_scp_domain);
+
+static const struct udevice_id mt8365_power_domain_ids[] = {
+ {
+ .compatible = "mediatek,mt8365-power-controller",
+ .data = (ulong)&mt8365_scp_soc_data,
+ },
+ { /* sentinel */ }
+};
+
+U_BOOT_DRIVER(mt8365_power_domain) = {
+ .name = "mt8365_power_domain",
+ .id = UCLASS_POWER_DOMAIN,
+ .ops = &mtk_power_domain_ops,
+ .probe = mtk_power_controller_probe,
+ .of_match = mt8365_power_domain_ids,
+ .priv_auto = sizeof(struct mtk_scpsys),
+};
--
2.55.0
