The DBSC5 DRAM controller protects DRAM content using inline ECC. The current set of carveouts follows SoC documentation, which describes the three trailing carveouts as larger than the rest.
Both the downstream IPL and mainline U-Boot on RSIP configure the ECC carveouts to the same size for all eight carveouts. Align the carveout sizes with the controller configuration set by the bootloader. This makes 1638 MiB of DRAM available for each of the three carveouts, which adds up to a total of 4915 MiB of newly accessible DRAM on this platform with this fix. Making this memory available does not pose a danger, since the current set of carveouts were carefully set to a larger size to prevent any possible issues until a confirmation from the hardware team become available, that it is safe to apply these less restrictive settings. Equivalent Linux kernel fix is posted at https://lore.kernel.org/linux-arm-kernel/[email protected]/ Signed-off-by: Marek Vasut <[email protected]> --- Cc: Nobuhiro Iwamatsu <[email protected]> Cc: Tom Rini <[email protected]> Cc: [email protected] --- arch/arm/dts/r8a78000-ironhide-u-boot.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm/dts/r8a78000-ironhide-u-boot.dtsi b/arch/arm/dts/r8a78000-ironhide-u-boot.dtsi index 2dc8ad7aa6b..cfa39f7858d 100644 --- a/arch/arm/dts/r8a78000-ironhide-u-boot.dtsi +++ b/arch/arm/dts/r8a78000-ironhide-u-boot.dtsi @@ -95,18 +95,18 @@ no-map; }; - ecc@1a66660000 { - reg = <0x1a 0x66660000 0x0 0x999a0000>; + ecc@1acccc0000 { + reg = <0x1a 0xcccc0000 0x0 0x33340000>; no-map; }; - ecc@1c66660000 { - reg = <0x1c 0x66660000 0x0 0x999a0000>; + ecc@1ccccc0000 { + reg = <0x1c 0xcccc0000 0x0 0x33340000>; no-map; }; - ecc@1e66660000 { - reg = <0x1e 0x66660000 0x0 0x999a0000>; + ecc@1ecccc0000 { + reg = <0x1e 0xcccc0000 0x0 0x33340000>; no-map; }; }; -- 2.53.0
