Hi Alif,
On Tue, 09 Jun 2026 09:48:17 +0800, [email protected] wrote:
+&mmc {
+ status = "okay";
+
+ no-mmc;
+ disable-wp;
+ cap-sd-highspeed;
+ vmmc-supply = <&sd_emmc_power>;
+ vqmmc-supply = <&sd_io_1v8_reg>;
+ max-frequency = <200000000>;
+ sdhci-caps = <0x00000000 0x0000c800>;
Please also add the Premium SoCDK UHS capability flags next to
cap-sd-highspeed, matching socfpga_agilex5_socdk-u-boot.dtsi:
sd-uhs-sdr50;
sd-uhs-sdr104;
sdhci-caps-mask = <0x00002000 0x0000ff00>;
The Cadence PHY timing properties alone do not advertise UHS modes to
the MMC stack. Without these, MDK will not match the Premium UHS path
despite the commit claiming the same SD timing / UHS-I support. Please
re-test SD UHS on MDK after the change.
+#include "socfpga_agilex5_socdk.dts"
+
+&i2c3 {
Please override the board model in the leaf DTS. As written it still
inherits "SoCFPGA Agilex5 SoCDK" from the Premium include, which is
confusing for UART/boot triage. Something like:
/ {
model = "SoCFPGA Agilex5 Modular DevKit";
};
New files added:
- socfpga_agilex5_socdk_modular.dts: Main device tree for modular board
- socfpga_agilex5_socdk_modular-u-boot.dtsi: U-Boot specific additions
- configs/socfpga_agilex5_modular_defconfig: Modular board configuration
checkpatch warns that new files may need a MAINTAINERS update. If the
existing Agilex5 SoCDK wildcards already cover these paths, a short note
in the cover is enough; otherwise please add F: entries.
Please send a v3 with the UHS flags(and preferably the model string)
addressed.
Best regards,
Tien Fong
