On Sat, Sep 19, 2026 at 04:29:41AM +0800, Han Gao wrote:
> Use CIPA instead of CPA to clean and invalidate cache lines. This
> fixes stale DMA descriptors breaking USB enumeration on TH1520.
I guess this issue isn't present in mainline U-Boot yet, since we don't
have USB support for TH1520 currently? If so, please omit this part in
commit message, you could mention this below the --- line.
And it would be good to mention the meaning and full form
("th.dcache.*") of CPA/CIPA here, and attach a link to the documentation
of T-Head's extensions. As a fix, this also deserves a Fixes tag.
For the fix itself, it sounds correct. I had a brief look over several
architectures' flush_dcache_range(),
- The zicbom path on RISC-V makes use of cbo.flush, per the RISC-V
specification (Volume I, 19.6.1 Cache-Block Management Instructions),
a flush operation atomically performs a clean operation followed by an
invalidate operation.
- MIPS uses HIT_WRITEBACK_INV_D & HIT_WRITEBACK_INV_SD
- PowerPC implements flush_dcache_range() with dcbf, which is described
as "those locations are written to main storage and additional
locations in the block may be written to main storage. The block is
invalidated in the data caches of all/this (depending on memory
coherence) processors", matching the behavior of flush
(clean/writeback & invalidate).
- flush_dcache_range() is no-op on platforms other than
MPC85xx/MPC86xx, I guess coherency is guaranteed otherwise?
- ARMv8's flush_dcache_range() is also commented as "INvalidates range
in all levels of D-cache/unified cache"
So this fix aligns thead_cmo.c's behavior with other implementations.
With the commit message improved,
Reviewed-by: Yao Zi <[email protected]>
> Signed-off-by: Han Gao <[email protected]>
> ---
> arch/riscv/lib/thead_cmo.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/riscv/lib/thead_cmo.c b/arch/riscv/lib/thead_cmo.c
> index b8051e29e02b..763ff799eddd 100644
> --- a/arch/riscv/lib/thead_cmo.c
> +++ b/arch/riscv/lib/thead_cmo.c
> @@ -40,6 +40,6 @@ void flush_dcache_range(unsigned long start, unsigned long
> end)
> {
> register unsigned long i asm("a0") = start &
> ~(CONFIG_SYS_CACHELINE_SIZE - 1);
> for (; i < end; i += CONFIG_SYS_CACHELINE_SIZE)
> - __asm__ __volatile__(DCACHE_CPA_A0);
> + __asm__ __volatile__(DCACHE_CIPA_A0);
> __asm__ __volatile__(SYNC_S);
> }
Regards,
Yao Zi
