From: Chen-Yu Yeh <[email protected]> The CV180x/CV181x family has an additional DesignWare APB GPIO controller (PWR_GPIO) located in the always-on power domain at 0x5021000. Add the node so that boards can reference GPIOs in this bank, such as status LEDs.
Signed-off-by: Chen-Yu Yeh <[email protected]> Link: https://patch.msgid.link/[email protected] Signed-off-by: Inochi Amaoto <[email protected]> Signed-off-by: Chen Wang <[email protected]> [ upstream commit: 76237a509a0e91665c4d9c96b72a78ec66ea3fe4 ] (cherry picked from commit dc28678310443c294191632f6ec175a62d53e767) --- dts/upstream/src/riscv/sophgo/cv180x.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/dts/upstream/src/riscv/sophgo/cv180x.dtsi b/dts/upstream/src/riscv/sophgo/cv180x.dtsi index 06b0ce5a2db..8bf67ee4eca 100644 --- a/dts/upstream/src/riscv/sophgo/cv180x.dtsi +++ b/dts/upstream/src/riscv/sophgo/cv180x.dtsi @@ -448,6 +448,24 @@ status = "disabled"; }; + gpio4: gpio@5021000 { + compatible = "snps,dw-apb-gpio"; + reg = <0x5021000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + + porte: gpio-controller@0 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + ngpios = <32>; + reg = <0>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <SOC_PERIPHERAL_IRQ(54) IRQ_TYPE_LEVEL_HIGH>; + }; + }; + rtc@5025000 { compatible = "sophgo,cv1800b-rtc", "syscon"; reg = <0x5025000 0x2000>; -- 2.55.0
