Hi, > Add the 64MB GD25LB512MF (JEDEC ID 0xc8601a) to the SPI NOR ID table. >
Please confirm the datasheet link [1], and add Link: tag. > Signed-off-by: Jim Liu <[email protected]> > --- > drivers/mtd/spi/spi-nor-ids.c | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c > index 3e7096bd419..06794d5507a 100644 > --- a/drivers/mtd/spi/spi-nor-ids.c > +++ b/drivers/mtd/spi/spi-nor-ids.c > @@ -187,6 +187,8 @@ const struct flash_info spi_nor_ids[] = { > SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)}, > {INFO("gd25lb512", 0xc8671A, 0, 64 * 1024, 1024, SECT_4K | > SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)}, > + {INFO("gd25lb512mf", 0xc8601A, 0, 64 * 1024, 1024, SECT_4K | > + SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)}, The chip has 4-bit BP and TB that not supported in u-boot. Probably the other existing chips have the same issue, but I'm reluctant to add a new chip with HAS_LOCK flag when it is known not to work... Thanks, Takahiro > {INFO("gd55lb01g", 0xc8671B, 0, 64 * 1024, 2048, SECT_4K | > SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)}, > {INFO("gd55lb02g", 0xc8671C, 0, 64 * 1024, 4096, SECT_4K | > -- > 2.34.1 [1] https://download.gigadevice.com/Datasheet/DS-01014-GD25LB512MF-Rev1.1.pdf
