Most of the simple display pipeline components share the same probe and enable sequence: remap the register window and enable a bulk of clocks. Add the mtk_disp_comp helpers holding this boilerplate so each component driver only has to provide its own component-specific programming.
The components which are DMA masters also need the SMI larb feeding them ungated, so add the lookup resolving that larb from their "iommus" property; the enable and disable helpers take care of it from there. Signed-off-by: Julien Stephan <[email protected]> --- drivers/video/mediatek/mtk_disp_comp.c | 123 +++++++++++++++++++++++++++++++++ drivers/video/mediatek/mtk_disp_comp.h | 95 +++++++++++++++++++++++++ 2 files changed, 218 insertions(+) diff --git a/drivers/video/mediatek/mtk_disp_comp.c b/drivers/video/mediatek/mtk_disp_comp.c new file mode 100644 index 00000000000..f9eb9e00de6 --- /dev/null +++ b/drivers/video/mediatek/mtk_disp_comp.c @@ -0,0 +1,123 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * MediaTek display pipeline component helpers + * + * Copyright (c) 2026 BayLibre, SAS. + * Author: Julien Stephan <[email protected]> + */ + +#include <asm/io.h> +#include <clk.h> +#include <dm.h> +#include <dm/device_compat.h> +#include <dm/ofnode.h> +#include <dt-bindings/memory/mtk-memory-port.h> +#include <errno.h> +#include <mtk_smi.h> + +#include "mtk_disp_comp.h" + +void mtk_disp_comp_write(struct udevice *dev, u32 offset, u32 val) +{ + struct mtk_disp_comp_priv *priv = dev_get_priv(dev); + + writel(val, priv->base + offset); +} + +void mtk_disp_comp_update(struct udevice *dev, u32 offset, u32 val, u32 mask) +{ + struct mtk_disp_comp_priv *priv = dev_get_priv(dev); + void __iomem *reg = priv->base + offset; + u32 tmp; + + tmp = readl(reg); + tmp = (tmp & ~mask) | (val & mask); + writel(tmp, reg); +} + +int mtk_disp_comp_enable(struct udevice *dev) +{ + struct mtk_disp_comp_priv *priv = dev_get_priv(dev); + int ret; + + /* ungate the feeding SMI larb first, if any */ + if (priv->larb) { + ret = mtk_smi_larb_enable(priv->larb); + if (ret) + return ret; + } + + ret = clk_enable_bulk(&priv->clk_bulk); + if (ret) { + dev_err(dev, "failed to enable clocks: %d\n", ret); + if (priv->larb) + mtk_smi_larb_disable(priv->larb); + return ret; + } + + return 0; +} + +int mtk_disp_comp_disable(struct udevice *dev) +{ + struct mtk_disp_comp_priv *priv = dev_get_priv(dev); + int ret; + + ret = clk_disable_bulk(&priv->clk_bulk); + if (ret) + dev_err(dev, "failed to disable clocks: %d\n", ret); + + if (priv->larb) + mtk_smi_larb_disable(priv->larb); + + return ret; +} + +int mtk_disp_comp_get_larb(struct udevice *dev) +{ + struct mtk_disp_comp_priv *priv = dev_get_priv(dev); + struct ofnode_phandle_args args; + ofnode iommu, node; + u32 larb_id, id; + int i, ret; + + ret = dev_read_phandle_with_args(dev, "iommus", "#iommu-cells", 0, 0, + &args); + if (ret) { + dev_err(dev, "cannot parse iommus: %d\n", ret); + return ret; + } + iommu = args.node; + larb_id = MTK_M4U_TO_LARB(args.args[0]); + + for (i = 0; ; i++) { + node = ofnode_parse_phandle(iommu, "mediatek,larbs", i); + if (!ofnode_valid(node)) { + dev_err(dev, "no larb %u in iommu\n", larb_id); + return -ENODEV; + } + if (!ofnode_read_u32(node, "mediatek,larb-id", &id) && + id == larb_id) + break; + } + + return uclass_get_device_by_ofnode(UCLASS_MEMORY, node, &priv->larb); +} + +int mtk_disp_comp_probe(struct udevice *dev) +{ + struct mtk_disp_comp_priv *priv = dev_get_priv(dev); + int ret; + + priv->base = dev_remap_addr(dev); + if (!priv->base) + return -EINVAL; + + ret = clk_get_bulk(dev, &priv->clk_bulk); + if (ret) { + dev_err(dev, "failed to get clocks: %d\n", ret); + return ret; + } + + return 0; +} diff --git a/drivers/video/mediatek/mtk_disp_comp.h b/drivers/video/mediatek/mtk_disp_comp.h new file mode 100644 index 00000000000..8214af38b27 --- /dev/null +++ b/drivers/video/mediatek/mtk_disp_comp.h @@ -0,0 +1,95 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * MediaTek display pipeline component helpers + * + * Copyright (c) 2026 BayLibre, SAS. + * Author: Julien Stephan <[email protected]> + */ + +#ifndef _MTK_DISP_COMP_H +#define _MTK_DISP_COMP_H + +#include <clk.h> + +struct udevice; + +/** + * struct mtk_disp_comp_priv - common state of a display pipeline component + * @base: register window of the component + * @clk_bulk: clocks of the component + * @larb: optional SMI larb device (UCLASS_MEMORY), enabled and disabled + * together with the component. Only the RDMAs, which are the DMA + * masters of this pipeline, have one. + */ +struct mtk_disp_comp_priv { + void __iomem *base; + struct clk_bulk clk_bulk; + struct udevice *larb; +}; + +/** + * mtk_disp_comp_probe() - probe a display pipeline component + * @dev: component device, whose private data starts with a + * struct mtk_disp_comp_priv + * + * Map the first register window of the component and get its clocks. + * + * Return: 0 on success, or a negative error code + */ +int mtk_disp_comp_probe(struct udevice *dev); + +/** + * mtk_disp_comp_get_larb() - resolve the SMI larb behind a DMA master + * @dev: component device + * + * A DMA master component reaches DRAM through an SMI larb, which must be + * ungated for its accesses. The component points at its IOMMU (M4U) port + * through "iommus", and MTK_M4U_TO_LARB() extracts the larb id from that + * port. Resolve the matching larb in the IOMMU's "mediatek,larbs" list by + * its "mediatek,larb-id", so that mtk_disp_comp_enable() and + * mtk_disp_comp_disable() then enable and disable it together with the + * component. + * + * Return: 0 on success, or a negative error code + */ +int mtk_disp_comp_get_larb(struct udevice *dev); + +/** + * mtk_disp_comp_enable() - enable a display pipeline component + * @dev: component device + * + * Ungate the SMI larb of the component, if any, then enable its clocks. + * + * Return: 0 on success, or a negative error code + */ +int mtk_disp_comp_enable(struct udevice *dev); + +/** + * mtk_disp_comp_disable() - disable a display pipeline component + * @dev: component device + * + * Undo mtk_disp_comp_enable(): disable the clocks of the component, then + * gate its SMI larb, if any. + * + * Return: 0 on success, or a negative error code + */ +int mtk_disp_comp_disable(struct udevice *dev); + +/** + * mtk_disp_comp_write() - write a component register + * @dev: component device + * @offset: register offset in the component register window + * @val: value to write + */ +void mtk_disp_comp_write(struct udevice *dev, u32 offset, u32 val); + +/** + * mtk_disp_comp_update() - update some bits of a component register + * @dev: component device + * @offset: register offset in the component register window + * @val: new value of the bits in @mask + * @mask: bits to update + */ +void mtk_disp_comp_update(struct udevice *dev, u32 offset, u32 val, u32 mask); + +#endif /* _MTK_DISP_COMP_H */ -- 2.55.0
