Subsystem clock blocks only provide gates, and every one of them declares the very same struct mtk_clk_tree boilerplate. clk-mt8189.c already hides it behind a local GATE_CLK_TREE() macro.
Move that macro to clk-mtk.h as MTK_GATE_CLK_TREE() so that the other MediaTek clock drivers can use it too. The array of external clock rates and the tree name are now passed explicitly, so that they can be grepped more easily now that the macro is defined in another file. While at it, move the clk-mt8189.c declarations above the of_match tables, next to the other clock trees, in preparation for merging the clock drivers into a single one. No functional change. Signed-off-by: Julien Stephan <[email protected]> --- drivers/clk/mediatek/clk-mt8189.c | 25 ++++++++----------------- drivers/clk/mediatek/clk-mtk.h | 22 ++++++++++++++++++++++ 2 files changed, 30 insertions(+), 17 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt8189.c b/drivers/clk/mediatek/clk-mt8189.c index 3724dffcc3a..05e5593c714 100644 --- a/drivers/clk/mediatek/clk-mt8189.c +++ b/drivers/clk/mediatek/clk-mt8189.c @@ -1970,6 +1970,14 @@ static const struct mtk_clk_tree mt8189_vlpckgen_clk_tree = { .type = MTK_CLK_TREE_VLP_CK, }; +MTK_GATE_CLK_TREE(ext_clock_rates, perao_clks_tree, perao_clks); +MTK_GATE_CLK_TREE(ext_clock_rates, imp_clks_tree, imp_clks); +MTK_GATE_CLK_TREE(ext_clock_rates, mm_clks_tree, mm_clks); +MTK_GATE_CLK_TREE(ext_clock_rates, mminfra_config_clks_tree, mminfra_config_clks); +MTK_GATE_CLK_TREE(ext_clock_rates, ufs_config_ao_clks_tree, ufs_config_ao_clks); +MTK_GATE_CLK_TREE(ext_clock_rates, ufs_config_pdn_clks_tree, ufs_config_pdn_clks); +MTK_GATE_CLK_TREE(ext_clock_rates, vlpcfg_ao_clks_tree, vlpcfg_ao_clks); + static const struct udevice_id mt8189_apmixed[] = { { .compatible = "mediatek,mt8189-apmixedsys", @@ -1994,23 +2002,6 @@ static const struct udevice_id mt8189_vlpckgen[] = { { } }; -#define GATE_CLK_TREE(_name) \ -static const struct mtk_clk_tree _name##_tree = { \ - .ext_clk_rates = ext_clock_rates, \ - .num_ext_clks = ARRAY_SIZE(ext_clock_rates), \ - .gates = _name, \ - .num_gates = ARRAY_SIZE(_name), \ - .gates_offs = _name[0].id, \ -} - -GATE_CLK_TREE(perao_clks); -GATE_CLK_TREE(imp_clks); -GATE_CLK_TREE(mm_clks); -GATE_CLK_TREE(mminfra_config_clks); -GATE_CLK_TREE(ufs_config_ao_clks); -GATE_CLK_TREE(ufs_config_pdn_clks); -GATE_CLK_TREE(vlpcfg_ao_clks); - static const struct udevice_id of_match_mt8189_clk_gate[] = { { .compatible = "mediatek,mt8189-peri-ao", .data = (ulong)&perao_clks_tree }, { .compatible = "mediatek,mt8189-iic-wrap", .data = (ulong)&imp_clks_tree }, diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h index 9244542a2a5..fc7b7955228 100644 --- a/drivers/clk/mediatek/clk-mtk.h +++ b/drivers/clk/mediatek/clk-mtk.h @@ -8,6 +8,7 @@ #define __DRV_CLK_MTK_H #include <linux/bitops.h> +#include <linux/kernel.h> #define MHZ (1000 * 1000) @@ -274,6 +275,27 @@ struct mtk_clk_tree { enum mtk_clk_tree_type type; }; +/** + * MTK_GATE_CLK_TREE() - declare a clock tree made of gates only + * @_ext_rates: array holding the rates of the external clocks + * @_tree: name of the struct mtk_clk_tree to declare + * @_gates: struct mtk_gate array backing the tree + * + * Most subsystem clock blocks only provide gates, whose IDs are + * contiguous and start at the ID of the first entry of @_gates. + * + * @_tree is declared static, so this must be used from the file + * defining @_gates. + */ +#define MTK_GATE_CLK_TREE(_ext_rates, _tree, _gates) \ + static const struct mtk_clk_tree _tree = { \ + .ext_clk_rates = _ext_rates, \ + .num_ext_clks = ARRAY_SIZE(_ext_rates), \ + .gates = _gates, \ + .num_gates = ARRAY_SIZE(_gates), \ + .gates_offs = _gates[0].id, \ + } + struct mtk_clk_priv { void __iomem *base; const struct mtk_clk_tree *tree; -- 2.55.0
