On Tue, Sep 29, 2026 at 07:59:44PM +0200, Vincent Jardin wrote: > + Initial conditions: > + > + - PLLS must be fed a reference clock from which the 10.3125 GHz > + clock net can be derived: 161.1328125 MHz, which 2x40g, > + 40g4x10g and 100g4x10g program PLLS for. Protocol 13 keeps PLLS > + powered down, so nothing checks that clock before these modes > + power it up: the board has to provide it.
Same comments as for patch 8, really. "A reference clock from which 10.3125 GHz clock net can be derived" sounds like it includes 156.25 MHz too, but the code is hardcoded for 161.1328125 MHz. I had to go look at the code to check, so I don't think it's sufficiently clear for a README yet. (I know it was my suggestion to phrase this way, but in v4 I didn't yet have a full overview of the assumptions you are making in the code)
