From: Igor Velkov <[email protected]> board_ahci_enable() sets the DRAM windows and the regret bit only at MVEBU_SATA0_BASE, the first controller (sata@a8000), but the generic AHCI driver calls it before probing each controller. On Armada 388 the second controller, sata@e0000, is left without these windows, so its DMA does not reach DRAM: the link comes up, the first command never completes and scsi scan hangs.
Use the address of the controller being probed. MVEBU_SATA0_BASE has no other user, drop it. Tested on Helios4, whose disk is on the second controller: without this change scsi scan hangs; with it the disk is found, and blocks read in U-Boot have the same CRC32 as when read from Linux. Signed-off-by: Igor Velkov <[email protected]> --- arch/arm/mach-mvebu/cpu.c | 7 +++++-- arch/arm/mach-mvebu/include/mach/soc.h | 1 - 2 files changed, 5 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-mvebu/cpu.c b/arch/arm/mach-mvebu/cpu.c index 09a0292699c..c13b9d70bfd 100644 --- a/arch/arm/mach-mvebu/cpu.c +++ b/arch/arm/mach-mvebu/cpu.c @@ -6,6 +6,7 @@ #include <config.h> #include <ahci.h> #include <cpu_func.h> +#include <dm.h> #include <init.h> #include <linux/bitops.h> #include <linux/delay.h> @@ -609,8 +610,10 @@ static void ahci_mvebu_regret_option(void __iomem *base) int board_ahci_enable(struct udevice *dev) { - ahci_mvebu_mbus_config((void __iomem *)MVEBU_SATA0_BASE); - ahci_mvebu_regret_option((void __iomem *)MVEBU_SATA0_BASE); + void __iomem *base = dev_remap_addr(dev); + + ahci_mvebu_mbus_config(base); + ahci_mvebu_regret_option(base); return 0; } diff --git a/arch/arm/mach-mvebu/include/mach/soc.h b/arch/arm/mach-mvebu/include/mach/soc.h index 33fdfd6d6c1..3ae5cffb669 100644 --- a/arch/arm/mach-mvebu/include/mach/soc.h +++ b/arch/arm/mach-mvebu/include/mach/soc.h @@ -77,7 +77,6 @@ #define MVEBU_USB20_BASE (MVEBU_REGISTER(0x58000)) #define MVEBU_REG_PCIE0_BASE (MVEBU_REGISTER(0x80000)) #define MVEBU_AXP_SATA_BASE (MVEBU_REGISTER(0xa0000)) -#define MVEBU_SATA0_BASE (MVEBU_REGISTER(0xa8000)) #define MVEBU_NAND_BASE (MVEBU_REGISTER(0xd0000)) #define MVEBU_SDIO_BASE (MVEBU_REGISTER(0xd8000)) #define MVEBU_LCD_BASE (MVEBU_REGISTER(0xe0000)) -- 2.43.0
