show_clks() prints information about the clock tree such as the rates of
various clocks. While doing this it gets the rate via clk_get_rate() and
stores it in an unsigned 32 bit integer variable. This limits the clock
rate to 4294967295 (or around 4.2GHz). If a clock rate exceeds this then
"clk dump" will print a rate which has wrapped around the unsigned 32
bit integer.
This was observed in the clock tree of an SoC ADI is currently bringing
up (the ADSP-SC846):
=> clk dump
...
cgu1_vco 505032704
cgu1_pllclk 2400000000
cclk2_1 1600000000
dclk1_1 960000000
...
In the above the VCO clock should have a rate of 4.8GHz via:
VCO = SYS_CLKIN * MSEL * 2 = 25MHz * 96 * 2 = 4,800,000,000 Hz. However,
4,800,000,000 truncated to 32 bits is 505032704, which is the value
reported above.
To fix this issue change the type of "rate" to ulong to match the
return value of clk_get_rate() also change the format specifier to
%lu to accommodate the type change.
Fixes: aeeb2e6d9c67 ("clk: support clk tree dump")
Signed-off-by: Qasim Ijaz <[email protected]>
---
cmd/clk.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/cmd/clk.c b/cmd/clk.c
index 2fc834e5549..3c816a41730 100644
--- a/cmd/clk.c
+++ b/cmd/clk.c
@@ -15,7 +15,7 @@ static void show_clks(struct udevice *dev, int depth, int
last_flag)
int i, is_last;
struct udevice *child;
struct clk *clkp, *parent;
- u32 rate;
+ ulong rate;
clkp = dev_get_clk_ptr(dev);
if (clkp) {
@@ -25,7 +25,7 @@ static void show_clks(struct udevice *dev, int depth, int
last_flag)
depth++;
rate = clk_get_rate(clkp);
- printf(" %-12u %8d ", rate, clkp->enable_count);
+ printf(" %-12lu %8d ", rate, clkp->enable_count);
for (i = depth; i >= 0; i--) {
is_last = (last_flag >> i) & 1;
--
2.43.0
