Import the MR-NAVQ95 device tree file from upstream Linux. The DTS
content is identical to the version accepted upstream and merged into
linux-next. A subsequent change will switch the board to OF_UPSTREAM
once the DTS appears in devicetree-rebasing.
Sync with Linux commit 3893cb7b467476878dc2de1b8b313f60ffa6c369 ("arm64:
dts: freescale: add MR-NAVQ95 basic board support") merged into
linux-next.
Signed-off-by: Elena Popa <[email protected]>
---
arch/arm/dts/imx95-navq.dts | 228 ++++++++++++++++++++++++++++++++++++
1 file changed, 228 insertions(+)
create mode 100644 arch/arm/dts/imx95-navq.dts
diff --git a/arch/arm/dts/imx95-navq.dts b/arch/arm/dts/imx95-navq.dts
new file mode 100644
index 00000000000..7860c113e9e
--- /dev/null
+++ b/arch/arm/dts/imx95-navq.dts
@@ -0,0 +1,228 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2026 NXP
+ */
+
+/dts-v1/;
+
+#include "imx95.dtsi"
+
+/ {
+ model = "NXP MR-NAVQ95";
+ compatible = "fsl,imx95-navq", "fsl,imx95";
+
+ aliases {
+ ethernet0 = &enetc_port0;
+ mmc0 = &usdhc1;
+ mmc1 = &usdhc2;
+ serial0 = &lpuart1;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ /* actual size filled in by the bootloader */
+ reg = <0x0 0x80000000 0 0x80000000>;
+ };
+
+ reg_usdhc2_vmmc: regulator-usdhc2 {
+ compatible = "regulator-fixed";
+ bootph-pre-ram;
+ enable-active-high;
+ gpios = <&gpio3 7 GPIO_ACTIVE_HIGH>;
+ off-on-delay-us = <12000>;
+ pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
+ pinctrl-names = "default";
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <3300000>;
+ regulator-name = "VDD_SD2_3V3";
+ };
+};
+
+&edma1 {
+ /* owned by M7 */
+ status = "reserved";
+};
+
+&edma2 {
+ /* channels 30-63 owned by M7 */
+ dma-channels = <30>;
+};
+
+&enetc_port0 {
+ phy-handle = <ðphy0>;
+ phy-mode = "rgmii-id";
+ pinctrl-0 = <&pinctrl_enetc0>;
+ pinctrl-names = "default";
+
+ status = "okay";
+};
+
+&lpi2c3 {
+ clock-frequency = <400000>;
+ pinctrl-0 = <&pinctrl_lpi2c3>;
+ pinctrl-names = "default";
+
+ status = "okay";
+
+ i2c3_gpio_expander_21: gpio-expander@21 {
+ compatible = "nxp,pcal6408";
+ reg = <0x21>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ interrupt-parent = <&gpio4>;
+ interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-0 = <&pinctrl_i2c3_gpio_expander_21>;
+ pinctrl-names = "default";
+ };
+};
+
+&lpuart1 {
+ bootph-pre-ram;
+ pinctrl-0 = <&pinctrl_uart1>;
+ pinctrl-names = "default";
+
+ status = "okay";
+};
+
+&netc_blk_ctrl {
+ status = "okay";
+};
+
+&netc_emdio {
+ pinctrl-0 = <&pinctrl_emdio>;
+ pinctrl-names = "default";
+
+ status = "okay";
+
+ ethphy0: ethernet-phy@1 {
+ compatible = "ethernet-phy-id001c.c916";
+ reg = <1>;
+ reset-assert-us = <10000>;
+ reset-deassert-us = <80000>;
+ reset-gpios = <&i2c3_gpio_expander_21 1 GPIO_ACTIVE_LOW>;
+ realtek,clkout-disable;
+ };
+};
+
+&scmi_iomuxc {
+ pinctrl_emdio: emdiogrp {
+ fsl,pins = <IMX95_PAD_ENET2_MDC__NETCMIX_TOP_NETC_MDC
0x57e>,
+ <IMX95_PAD_ENET2_MDIO__NETCMIX_TOP_NETC_MDIO
0x97e>;
+ };
+
+ pinctrl_enetc0: enetc0grp {
+ fsl,pins = <IMX95_PAD_ENET1_TD3__NETCMIX_TOP_ETH0_RGMII_TD3
0x57e>,
+ <IMX95_PAD_ENET1_TD2__NETCMIX_TOP_ETH0_RGMII_TD2
0x57e>,
+ <IMX95_PAD_ENET1_TD1__NETCMIX_TOP_ETH0_RGMII_TD1
0x57e>,
+ <IMX95_PAD_ENET1_TD0__NETCMIX_TOP_ETH0_RGMII_TD0
0x57e>,
+
<IMX95_PAD_ENET1_TX_CTL__NETCMIX_TOP_ETH0_RGMII_TX_CTL 0x57e>,
+ <IMX95_PAD_ENET1_TXC__NETCMIX_TOP_ETH0_RGMII_TX_CLK
0x58e>,
+
<IMX95_PAD_ENET1_RX_CTL__NETCMIX_TOP_ETH0_RGMII_RX_CTL 0x57e>,
+ <IMX95_PAD_ENET1_RXC__NETCMIX_TOP_ETH0_RGMII_RX_CLK
0x58e>,
+ <IMX95_PAD_ENET1_RD0__NETCMIX_TOP_ETH0_RGMII_RD0
0x57e>,
+ <IMX95_PAD_ENET1_RD1__NETCMIX_TOP_ETH0_RGMII_RD1
0x57e>,
+ <IMX95_PAD_ENET1_RD2__NETCMIX_TOP_ETH0_RGMII_RD2
0x57e>,
+ <IMX95_PAD_ENET1_RD3__NETCMIX_TOP_ETH0_RGMII_RD3
0x57e>;
+ };
+
+ pinctrl_i2c3_gpio_expander_21: i2c3gpioexpander21grp {
+ fsl,pins = <IMX95_PAD_ENET2_RD3__GPIO4_IO_BIT27
0x31e>;
+ };
+
+ pinctrl_lpi2c3: lpi2c3grp {
+ fsl,pins = <IMX95_PAD_GPIO_IO28__LPI2C3_SDA
0x40000b9e>,
+ <IMX95_PAD_GPIO_IO29__LPI2C3_SCL
0x40000b9e>;
+ };
+
+ pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
+ bootph-pre-ram;
+ fsl,pins = <IMX95_PAD_SD2_RESET_B__GPIO3_IO_BIT7
0x31e>;
+ };
+
+ pinctrl_uart1: uart1grp {
+ bootph-pre-ram;
+ fsl,pins = <IMX95_PAD_UART1_RXD__AONMIX_TOP_LPUART1_RX
0x31e>,
+ <IMX95_PAD_UART1_TXD__AONMIX_TOP_LPUART1_TX
0x31e>;
+ };
+
+ pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
+ bootph-pre-ram;
+ fsl,pins = <IMX95_PAD_SD1_CLK__USDHC1_CLK
0x15fe>,
+ <IMX95_PAD_SD1_CMD__USDHC1_CMD
0x13fe>,
+ <IMX95_PAD_SD1_DATA0__USDHC1_DATA0
0x13fe>,
+ <IMX95_PAD_SD1_DATA1__USDHC1_DATA1
0x13fe>,
+ <IMX95_PAD_SD1_DATA2__USDHC1_DATA2
0x13fe>,
+ <IMX95_PAD_SD1_DATA3__USDHC1_DATA3
0x13fe>,
+ <IMX95_PAD_SD1_DATA4__USDHC1_DATA4
0x13fe>,
+ <IMX95_PAD_SD1_DATA5__USDHC1_DATA5
0x13fe>,
+ <IMX95_PAD_SD1_DATA6__USDHC1_DATA6
0x13fe>,
+ <IMX95_PAD_SD1_DATA7__USDHC1_DATA7
0x13fe>,
+ <IMX95_PAD_SD1_STROBE__USDHC1_STROBE
0x15fe>;
+ };
+
+ pinctrl_usdhc1: usdhc1grp {
+ bootph-pre-ram;
+ fsl,pins = <IMX95_PAD_SD1_CLK__USDHC1_CLK
0x158e>,
+ <IMX95_PAD_SD1_CMD__USDHC1_CMD
0x138e>,
+ <IMX95_PAD_SD1_DATA0__USDHC1_DATA0
0x138e>,
+ <IMX95_PAD_SD1_DATA1__USDHC1_DATA1
0x138e>,
+ <IMX95_PAD_SD1_DATA2__USDHC1_DATA2
0x138e>,
+ <IMX95_PAD_SD1_DATA3__USDHC1_DATA3
0x138e>,
+ <IMX95_PAD_SD1_DATA4__USDHC1_DATA4
0x138e>,
+ <IMX95_PAD_SD1_DATA5__USDHC1_DATA5
0x138e>,
+ <IMX95_PAD_SD1_DATA6__USDHC1_DATA6
0x138e>,
+ <IMX95_PAD_SD1_DATA7__USDHC1_DATA7
0x138e>,
+ <IMX95_PAD_SD1_STROBE__USDHC1_STROBE
0x158e>;
+ };
+
+ pinctrl_usdhc2_gpio: usdhc2gpiogrp {
+ bootph-pre-ram;
+ fsl,pins = <IMX95_PAD_SD2_CD_B__GPIO3_IO_BIT0
0x31e>;
+ };
+
+ pinctrl_usdhc2: usdhc2grp {
+ bootph-pre-ram;
+ fsl,pins = <IMX95_PAD_SD2_CLK__USDHC2_CLK
0x158e>,
+ <IMX95_PAD_SD2_CMD__USDHC2_CMD
0x138e>,
+ <IMX95_PAD_SD2_DATA0__USDHC2_DATA0
0x138e>,
+ <IMX95_PAD_SD2_DATA1__USDHC2_DATA1
0x138e>,
+ <IMX95_PAD_SD2_DATA2__USDHC2_DATA2
0x138e>,
+ <IMX95_PAD_SD2_DATA3__USDHC2_DATA3
0x138e>,
+ <IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT
0x51e>;
+ };
+};
+
+&usdhc1 {
+ bootph-pre-ram;
+ bus-width = <8>;
+ no-sd;
+ no-sdio;
+ non-removable;
+ pinctrl-0 = <&pinctrl_usdhc1>;
+ pinctrl-1 = <&pinctrl_usdhc1>;
+ pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
+ pinctrl-3 = <&pinctrl_usdhc1>;
+ pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
+
+ status = "okay";
+};
+
+&usdhc2 {
+ bootph-pre-ram;
+ bus-width = <4>;
+ cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>;
+ pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-1 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-2 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-3 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
+ vmmc-supply = <®_usdhc2_vmmc>;
+
+ status = "okay";
+};
--
2.43.0
